Version 1 Postmortem & Proposal for future
Posted: Thu Feb 08, 2024 12:51 am
Hello!
I reviewed the original "Building my dream computer - Part I" video and tried to gather the original requirements into a somewhat cohesive list. I also tried to prioritize requirements where possible.
I'm sure some of those requirements have shifted over time, and it looks like the project has managed to garner a bit of a community. Still, one of the most glaring problems with the current version is that it ended up with a $350 price tag, which puts it well north of a MiSTER system which can essentially emulate the X16 along with many other systems.
Obviously, the no FPGA rule was eventually dropped, but I don't think the potential of the FPGA was fully realized. For example, as far as I understand, the VERA board is capable of implementing a sound chip making the Yamaha chip a bit redundant.
The thing about FPGAs is: They shouldn’t require any deeper understanding, however; they do allow for a deeper understanding of the system. I could put an FPGA with a config ROM and voltage regulator on a PCB with 40 through-hole pins and cover the whole thing with black plastic and you wouldn't even know it's not an authentic 6502 or whatever. However, I could also expose the config ROM so that onece the user learns BASIC then assembly, they can move on to HDL if they want to. It lets them go further down the rabbit hole, but it doesn't force them to.
Here are some nubers:
A 6502 core takes up <700 logic elements running over 10 MHz (source)
A 32-bit RISC-V core (a more relevant architecture to learn) can use about 900 logic elements running several hundred MHz (source)
Some crazy people have even managed to squeeze a RISC-V CPU down to <200 Logic elements.
The 6502 is actually pretty hard to implement effeiciently in an FPGA. Other 8-bit designs from Lattice, Xilinx, and Intel use in the 200 Logic element range and run in the 50+ MHz range even on low end hardware.
I haven't found many good resources for the size of VIC-II implementations, but the VIC-II uses about twice the number of transistors, so ~1400 logic elements is a conservative estimate. Sound is generated in the tens of kHz, so a decent sound chip takes up practically no space on an FPGA.
All-in-all, I think someone could squeeze an entire C64 into a single $8 Lattice Ice-40 UP5K. If we wanted more room, we could jump up to a $12 LFE5U-12F with 12K logic elements, but it ironically doesn't have as much RAM (go figure). With that kind of system you not only introduce the resource constraints you're going after, but also the low cost.
I think, howerver, there's an even better move.
A company named Cologne Chip just realeased a new FPGA called GateMate. The cheapest chip goes for $16 in fairly low quatities and has the equivalent of 40k logic elements. To sweeten the deal, the company is all in on open-source tool-chains. If this was paired with a decent SoC, like the Milk-V duo, it would probably be possible to make a portable MiSTER-like system.
According to their website, there should be larger versions of the GateMate available very soon including a 160k LE variant which would make replacing the MiSTER easier (it has a 110k LE FPGA with fancy DSP units), but I think the MiSTER team could stand to optimize their cores. The last I checked, the system that takes up the most of MiSTER's logic is the NES (a little over 80% of the logic) because that core loads every possible cartridge mapper chip or something.
If we could get the MiSTER community's attention, that would be amazing.
Anyway, a single FPGA replacing all that logic is 100% the way to go. I think a RISC-V CPU would make more sense than a 6502. I also think there might be better languages than BASIC to start out with, but I haven't really done a survey.
I reviewed the original "Building my dream computer - Part I" video and tried to gather the original requirements into a somewhat cohesive list. I also tried to prioritize requirements where possible.
- Recreate the retro computing experience
Primarily focus on edutainment.- Emphasize
- Immediacy (plug & play)
- Documentation (w/ examples)
- Simplicity (BASIC, low abstraction)
- Close-to-Hardware (poke & push registers, assembly)
- Restrictions (limited RAM and CPU speed)
- Avoid
- Making people source old/unreliable/expensive tech
- Anything that makes the experience tedious
- Non-Standard interfaces
- Productivity Apps
- Emphasize
- Harbor a Community
- Affordable (<$100)
- Available ("off-the-shelf" parts)
- Usable (HDMI, USB?)
- Open Source? (Not stated in video, but seems obvious and important for building a community)
- No FPGAs or MCUs (no reason given)
- Must have a real 6502 CPU (no reason given & contradicts part 1:55 of the video)
- Must run Commodore BASIC (no reason given & contradicts part 1:55 of the video)
- Raspberry Pi is out (because it can run linux?)
I'm sure some of those requirements have shifted over time, and it looks like the project has managed to garner a bit of a community. Still, one of the most glaring problems with the current version is that it ended up with a $350 price tag, which puts it well north of a MiSTER system which can essentially emulate the X16 along with many other systems.
Obviously, the no FPGA rule was eventually dropped, but I don't think the potential of the FPGA was fully realized. For example, as far as I understand, the VERA board is capable of implementing a sound chip making the Yamaha chip a bit redundant.
The thing about FPGAs is: They shouldn’t require any deeper understanding, however; they do allow for a deeper understanding of the system. I could put an FPGA with a config ROM and voltage regulator on a PCB with 40 through-hole pins and cover the whole thing with black plastic and you wouldn't even know it's not an authentic 6502 or whatever. However, I could also expose the config ROM so that onece the user learns BASIC then assembly, they can move on to HDL if they want to. It lets them go further down the rabbit hole, but it doesn't force them to.
Here are some nubers:
A 6502 core takes up <700 logic elements running over 10 MHz (source)
A 32-bit RISC-V core (a more relevant architecture to learn) can use about 900 logic elements running several hundred MHz (source)
Some crazy people have even managed to squeeze a RISC-V CPU down to <200 Logic elements.
The 6502 is actually pretty hard to implement effeiciently in an FPGA. Other 8-bit designs from Lattice, Xilinx, and Intel use in the 200 Logic element range and run in the 50+ MHz range even on low end hardware.
I haven't found many good resources for the size of VIC-II implementations, but the VIC-II uses about twice the number of transistors, so ~1400 logic elements is a conservative estimate. Sound is generated in the tens of kHz, so a decent sound chip takes up practically no space on an FPGA.
All-in-all, I think someone could squeeze an entire C64 into a single $8 Lattice Ice-40 UP5K. If we wanted more room, we could jump up to a $12 LFE5U-12F with 12K logic elements, but it ironically doesn't have as much RAM (go figure). With that kind of system you not only introduce the resource constraints you're going after, but also the low cost.
I think, howerver, there's an even better move.
A company named Cologne Chip just realeased a new FPGA called GateMate. The cheapest chip goes for $16 in fairly low quatities and has the equivalent of 40k logic elements. To sweeten the deal, the company is all in on open-source tool-chains. If this was paired with a decent SoC, like the Milk-V duo, it would probably be possible to make a portable MiSTER-like system.
According to their website, there should be larger versions of the GateMate available very soon including a 160k LE variant which would make replacing the MiSTER easier (it has a 110k LE FPGA with fancy DSP units), but I think the MiSTER team could stand to optimize their cores. The last I checked, the system that takes up the most of MiSTER's logic is the NES (a little over 80% of the logic) because that core loads every possible cartridge mapper chip or something.
If we could get the MiSTER community's attention, that would be amazing.
Anyway, a single FPGA replacing all that logic is 100% the way to go. I think a RISC-V CPU would make more sense than a 6502. I also think there might be better languages than BASIC to start out with, but I haven't really done a survey.