Sprites per Scanline limits
Posted: Fri Feb 24, 2023 10:06 pm
Hi all,
I've been running some VERA simulations to try and get some insight into its behavior. One area I looked at is the sprites-per-scanline limit for the following configuration:
- 640x480 VGA mode
- Layer 0 and 1 enabled in 8bpp tile mode
- 8bpp sprites
These are the results I got:
- Max. 43 8x8 sprites/scanline.
- Max. 25 16x16 sprites/scanline.
- Max. 13 32x32 sprites/scanline.
- Max. 7 64x64 sprites/scanline.
The results may vary a bit depending on exactly which sprites IDs are enabled in the sprite attribute RAM. The VERA sprite renderer has an FSM that sequentially scans through the sprite attribute RAM to find the sprites that are active on the given scanline. For the simulation, I just used consecutive sprite IDs starting from 0.
With layers 0 and 1 disabled, the results are slightly better because there's less pressure on VERA's main RAM:
- Max. 53 8x8 sprites/scanline.
- Max. 29 16x16 sprites/scanline.
- Max. 15 32x32 sprites/scanline.
- Max. 8 64x64 sprites/scanline.
Has anybody been able to measure the sprites/scanline limits on an actual VERA FPGA?
I've been running some VERA simulations to try and get some insight into its behavior. One area I looked at is the sprites-per-scanline limit for the following configuration:
- 640x480 VGA mode
- Layer 0 and 1 enabled in 8bpp tile mode
- 8bpp sprites
These are the results I got:
- Max. 43 8x8 sprites/scanline.
- Max. 25 16x16 sprites/scanline.
- Max. 13 32x32 sprites/scanline.
- Max. 7 64x64 sprites/scanline.
The results may vary a bit depending on exactly which sprites IDs are enabled in the sprite attribute RAM. The VERA sprite renderer has an FSM that sequentially scans through the sprite attribute RAM to find the sprites that are active on the given scanline. For the simulation, I just used consecutive sprite IDs starting from 0.
With layers 0 and 1 disabled, the results are slightly better because there's less pressure on VERA's main RAM:
- Max. 53 8x8 sprites/scanline.
- Max. 29 16x16 sprites/scanline.
- Max. 15 32x32 sprites/scanline.
- Max. 8 64x64 sprites/scanline.
Has anybody been able to measure the sprites/scanline limits on an actual VERA FPGA?