The video part should make the pixel clock accessible
The video part should make the pixel clock accessible
A suggestion for the VERA graphics is to make a pixel clock pin available externally so that digital monitors can be used by adding an external A/D. Even better would of course be pixel clock + digital RGB using LVDS etc. This would enable TFT modules, DVI, HDMI etc with rock solid video at high resolutions.
One of the most messy matters to regenerate is the pixel clock. So this one-bit signal I would say is the most crucial.
The video part should make the pixel clock accessible
There are no available IOs on the FPGA to provide this signal.
The video part should make the pixel clock accessible
@Wavicle, maybe the clock generator is possible to piggyback and is in phase with the video?
The video part should make the pixel clock accessible
On 10/22/2022 at 12:58 AM, neutrino said:
@Wavicle, maybe the clock generator is possible to piggyback and is in phase with the video?
I am not sure what you mean. VERA uses an external 25MHz clock. It is used by VERA as a pixel clock, but due to physics and the FPGA's construction, it will be slightly out of phase with the VGA pixels.
The video part should make the pixel clock accessible
If the phase difference is constant it might work.