On 10/11/2021 at 6:26 AM, BruceMcF said:
I think it is important not to over-generalize here. There is an argument that it is not possible to build Dave's dream computer without a custom fabricated video chip, and the only feasible way to create a custom fabricated video chip at this scale is using an FPGA with the build in hardware that can be wired together to perform the process ...
... which is an argument about Dave's 8bit dream computer.
It is not an argument about an 8bit dream computer in general. If someone has a dream that can be satisfied with a pure tile display, or with a screenbuffer chip, there seem to be options that will work. It's the tile and hardware sprite implemented with a scanline by scanline rowbuffer display that requires either an FPGA to wire the circuit together or an MCU to emulate a notional custom fabricated chip.
So people shouldn't make unwarranted generalizations. It is certainly possible to dream different specific dreams and avoid the choice between an FPGA implementation and a software emulation of a notional chip.
As for that specific choice, for a system that has a design goal of being built to the extent possible with in production ASIC chips, I have no hesitation in arguing that a netlist wiring of hardware is closer to an ASIC chip than CPU emulating the behavior of a notional chip. But if somebody's dream was a "neo retro 6502 GEOS system", there are plenty of framebuffer chips to choose from.
So what you seem to me to be saying is that there is no possibility of satisfying the 'dream computer' objective of no FPGA because the choice for the X16 has been defined as it MUST have FPGA, not because it cant be done, rather the choice being made is that it should not be done. Whereas it could be done by simply designing the computer and optimizing the hardware, by which I mean a similar thing to cutting down software bloatware which everyone understands and then doing that same thing, but for hardware, for example, I watched Ben Eaters lovely video card tutorial for beginners and saw he seems to be using extra components that are not needed, perhaps for clarity ? for students. FPGA or ASIC seems to be a way to throw your hands up and say we don't have a hardware optimizer, so here is our bloatware hardware swept up into neat ASIC trashbag and Surface mounted onto the PCB for all time. I see it as akin to giving up.