Commander X16 audio capabilities

[xanthrou]

38 minutes ago, BruceMcF said:

The MHz should definitely be higher, z80 clocks are not like 6502 clocks, depending on whether the task is well or badly suited to the 6502, a z80 at 4.77MHz is similar to a 6502 at 1.5MHz to 2.5MHz. And the Z80 is designed to handle accessing things on slower buses than the z80 clock ... a 16v8 SLD would be enough to program the wait states required for an 8.33MHz Z80 to access a 1MHz or slower bus for a true SID chip, while if the FPGA SID simulator can be accessed at 4.77MHz or below (?? don't know, but that is the only reason I can see the z80 would be running so slow), you can cut the processor clock in half with just glue logic, triggered on the SID select line.

I prefer the glue logic one.

The speed then would be around 2.38 Mhz in order to communicate with FPGA SID.

And what about rest of the components?

[BruceMcF]

Wait, what? 2.38MHz is going the wrong way. That is getting as bad as the nearly useless 2MHz z80 in the C128. The point of the z80 control pin complex is to allow the z80 to run at a HIGHER clock speed than it's peripherals, relying on wait states to stretch the cycles that need to be stretched when accessing a slower peripheral, and running at the higher speed when operating internal to the processor or with SRAM.

What is the source of the maximum 4.77MHz access speed for the FPGA SID ... is it part of the timing for the correct frequencies on the settings?

[kelli217]

As far as I know, 4.77MHz is a 4/3 ratio to NTSC colorburst. If the Z80 isn't going to be closely tied to any video output circuitry, there's not much point in driving it at that clock speed. Might as well go for 8MHz operation.

[xanthrou]

9 hours ago, BruceMcF said:

Wait, what? 2.38MHz is going the wrong way. That is getting as bad as the nearly useless 2MHz z80 in the C128. The point of the z80 control pin complex is to allow the z80 to run at a HIGHER clock speed than it's peripherals, relying on wait states to stretch the cycles that need to be stretched when accessing a slower peripheral, and running at the higher speed when operating internal to the processor or with SRAM.



What is the source of the maximum 4.77MHz access speed for the FPGA SID ... is it part of the timing for the correct frequencies on the settings?

Okay, then the Z80 should be running 8.32MHz

[xanthrou]

2 hours ago, kelli217 said:

As far as I know, 4.77MHz is a 4/3 ratio to NTSC colorburst. If the Z80 isn't going to be closely tied to any video output circuitry, there's not much point in driving it at that clock speed. Might as well go for 8MHz operation.

Not really. It would be there for audio RAM, SID and CP/M modes.

[kelli217]

4 minutes ago, xanthrou said:

It would be there for audio RAM, SID and CP/M modes.

...okay? Why is 4.77 MHz, or 8.32, or whatever fractional frequency, necessary for the audio RAM, (FPGA-based) SID, and/or CP/M mode to function? I don't understand.

[BruceMcF]

8 hours ago, kelli217 said:

...okay? Why is 4.77 MHz, or 8.32, or whatever fractional frequency, necessary for the audio RAM, (FPGA-based) SID, and/or CP/M mode to function? I don't understand.

8.33MHz would be simplest, because it is the system clock frequency (50MHz/6). 16.67MHz would be most effective for CP/M if using a 20MHz rated z80, and would get the most done when used as an audio co-processor, but 8.33MHz would have been a reasonably quick CP/M system back in the day.

I've never seen specs for the FPGA SID emulator, but I would not be surprised if 4.77MHz is the clock for the FPGA in order to get the frequencies right in the SID emulation ... but the FPGA clock and the z80 clock doesn't have to be the same frequency.

[xanthrou]

32 minutes ago, BruceMcF said:

8.33MHz would be simplest, because it is the system clock frequency (50MHz/6). 16.67MHz would be most effective for CP/M if using a 20MHz rated z80, and would get the most done when used as an audio co-processor, but 8.33MHz would have been a reasonably quick CP/M system back in the day.



I've never seen specs for the FPGA SID emulator, but I would not be surprised if 4.77MHz is the clock for the FPGA in order to get the frequencies right in the SID emulation ... but the FPGA clock and the z80 clock doesn't have to be the same frequency.

Okay, so make it like that

The Z80 would operate 20Mhz as an audio co-processor and 16.67Mhz as a X16 CP/M processor.

The FPGA SID would be 4.77Mhz.

The speech synthesizer chip would operate 2.75Mhz.

 

[kelli217]

48 minutes ago, BruceMcF said:

8.33MHz would be simplest, because it is the system clock frequency (50MHz/6).

Now this is a detail that I hadn't yet grasped. I don't remember ever seeing it, but of course it's entirely possible that I just glossed over it. In the absence of realizing this information I thought the system clock was 8 MHz precisely, and that slower speeds were accomplished by simply halving the system clock.

[BruceMcF]

1 hour ago, kelli217 said:

Now this is a detail that I hadn't yet grasped. I don't remember ever seeing it, but of course it's entirely possible that I just glossed over it. In the absence of realizing this information I thought the system clock was 8 MHz precisely, and that slower speeds were accomplished by simply halving the system clock.

IIRC, VERA is like the Gameduino 1 in running on a 25MHz  external clock and 50MHz internally, so the "8Mhz" option for the 65C02 PHI2 frequency is really 8.33MHZ, 25Mhz/3. Two years ago they were trying to access the GPGA asynchronously, but that was buggy, so they went to a synchronous approach.

The 50Mhz is the dot clock on displaying the row that has just been generated while in parallel the next row is being generated in the other row buffer.