Commander X16 audio capabilities

[BruceMcF]

1 hour ago, m00dawg said:

I've been wondering about this - and perhaps should try to test this on my own, but since it's a buffer, bytes effectively "go away" right? As in, I can't just load the FIFO with 4kb one time and just keep triggering it (to play the same data)?

I haven't tested it, but on the information in the VERA Programmer Reference, it is indeed the case. It seems like it is a circular FIFO buffer, along the lines two indices without overflow, with he top index pointing to the first free slot, the bottom index pointing to the next slot to be consumed, if the two indices are equal, the buffer full bit is set and writes to the buffer are disallowed. The same subtraction result that tests for the two indices equal may also be tested for a difference of 1K bytes, which would trigger the low buffer interrupt if it is set.

IIUC, allowing the data to be re-used wouldn't be of much use anyway, even at quarter speed and with mono, 8-bit sound, so one byte per pulse, quarter speed is 12,207Hz, so 4K is about 1/3 of a second.

(Now, if there was a J1 in VERA, it could easily be programmed to play samples out of VERA's video RAM, but contention with the J1 for FPGA RAM access was why they dropped the original video FPGA in favor of the VERA design.)

[m00dawg]

4 minutes ago, BruceMcF said:

IIIUC, allowing the data to be re-used wouldn't be of much use anyway, even at quarter speed and with mono, 8-bit sound, so one byte per pulse, quarter speed is 12,207Hz, so 4K is about 1/3 of a second.

Hmm I would actually say that would be super useful, but only with an auto-loop, although 1/3rd of a second might be within the X16's ability to manage it. This would allow for chiptune waveforms. So not as much as digital sample (like those prevalent NES toms) but more like a very short single cycle (or few cycle) waveform - sort of like a programmable oscillator. Good examples of this are the GB's WAVE channel, the Famicom Disk System channel, TG16 channels, Renoise (a modern PC tracker) has this feature built in as well.

A single cycle though would be MUCH shorter than a .33 seconds though. But repeating the cycle for the full buffer might balance the requirement for the X16 to re-trigger it (given the Vera has no DPCM looping solution). In looking at the docs on how the DPCM works, I'm also not sure how well you can tune it - docs aren't clear on if the playback speed is granular enough to make notes with it.

 

[BruceMcF]

48kHz seems like it would be enough for a waveform. You might have to have multiple cycles to get a good splice point, but the source data for a more complex waveform of a single tone would indeed be substantially less than 4K. But keeping it filled would be the job of the CPU, unless an auxiliary bus mastering coprocessor was devised for the purpose.

[SlithyMatt]

When the FIFO runs out, it just stops. You have to write new data to the FIFO to get it to start playing again, no looping back around.

[xanthrou]

[xanthrou]

This is how my (poorly made) design of that daughterboard looks like.

Again, not a hardware expert, but I gave it a shot.

Any questions or criticisms?

[m00dawg]

4.77 MHz jumps out at me. That means there won't be an even multiple between it and the X16 bus. That won't solve all problems if it was, but is something of note. Also I'm not sure the SID can run at 4.77MHz either? Otherwise the only other thing I see is I'm not sure what the "sound from VERA" is? If it's the analog audio out from the X16, note while there might be an internal audio in header (at least it was discussed I think on the forums), I haven't heard anything about an internal audio out. Of course you can route the audio external to the case but something to consider there or perhaps I'm misreading that.

[xanthrou]

33 minutes ago, m00dawg said:

4.77 MHz jumps out at me. That means there won't be an even multiple between it and the X16 bus. That won't solve all problems if it was, but is something of note. Also I'm not sure the SID can run at 4.77MHz either? Otherwise the only other thing I see is I'm not sure what the "sound from VERA" is? If it's the analog audio out from the X16, note while there might be an internal audio in header (at least it was discussed I think on the forums), I haven't heard anything about an internal audio out. Of course you can route the audio external to the case but something to consider there or perhaps I'm misreading that.

If you correctly read it, this is an FPGA recreation of SID, which has all the bells and tolls of the original, and which is not VERA PSG.

So, the Z80 asked the 65c02 to reroute the DAC, YM2151 and VERA PSG/PCM to the former, so Z80 could place them onto dedicated sound RAM instead, plus few extras like mixed with FPGA SID and the speech synthesiser, freeing up RAM for other things.

Should I raise the MHz's higher or should I keep it as-is?

[m00dawg]

I'm not sure I can articulate the specifics better than Lorin. I can't remember quite where he posted it but it's somewhere on the forums. The frequency doesn't matter as much perhaps due to buffered circuitry but could make your life easier if it was a multiple. "buffer circuitry" here is a black box for me at the moment. The solve is not trivial but is solveable. But again Lorin explained the main issues better than I think I can.

[BruceMcF]

The MHz should definitely be higher, z80 clocks are not like 6502 clocks, depending on whether the task is well or badly suited to the 6502, a z80 at 4.77MHz is similar to a 6502 at 1.5MHz to 2.5MHz. And the Z80 is designed to handle accessing things on slower buses than the z80 clock ... a 16v8 SLD would be enough to program the wait states required for an 8.33MHz Z80 to access a 1MHz or slower bus for a true SID chip, while if the FPGA SID simulator can be accessed at 4.77MHz or below (?? don't know, but that is the only reason I can see the z80 would be running so slow), you can cut the processor clock in half with just glue logic, triggered on the SID select line.