Page 3 of 3

Dev board updates from Kevin Williams

Posted: Thu Dec 29, 2022 7:38 am
by neutrino

Any summary of the changes to the board?

 


Dev board updates from Kevin Williams

Posted: Thu Dec 29, 2022 8:49 am
by JimmyDansbo

I will try to give a summary of David's video.

Obviously, bodge wires from Prototype#3 are now gone

image.thumb.png.c66f21d77217bf3d93b7b87ddfc09c89.png

ATX Power connector has been moved from bottom of the board to the side of the board.

image.thumb.png.085ad121be6c0814da624c5ab1fef6c4.png

An extra 6522 used for userport as well as memory above 512K has been made optional and the team encourages developers to only develop for 512K memory as the next generation board may not even have the option to add more than the standard memory.

image.thumb.png.653fb977389427393a76238b73c473d4.png

An Audio header has been added to the board which enables developers to replace the onboard audio option with their own. Audio is also available at the normal card slots so it is possible to create a "normal" sound card for the system.

image.thumb.png.11372c413ebcb7d983356c610670e87b.png

An activity LED has been added, it indicates SD card access, but is software controllable and can be set to 256 brightness levels

image.thumb.png.316f0f7d1b20bb1e772191e6ea9ff508.png

The system speed selector (2, 4 or 8 MHz) is still present on this board, but it will most likely be removed as it has been confirmed that the system ROM can be programmed on the board without decreasing the clock rate.

Finally, on the back of the board. The audio and IEC/disk drive connector has been swapped.

image.png.3ce76780017926ead2582e89785d2b9b.png

If have forgotten something or have omitted some details, I am sure that others in the community can help out. Here is a different angle of the board

image.thumb.png.e933dd5052dbbf352cdabce366ac131d.png


Dev board updates from Kevin Williams

Posted: Thu Dec 29, 2022 11:23 am
by neutrino

Moving the ATX Power connector will likely be of serious consideration for any chassi makers.

An extra 6522 for userport.. maybe can enable burst transfers? What happened to the external-MCU-for-PS/2 ?

The system speed might be good to have around if older chips are used to swap the CPU or perhaps even faster CPU models becomes available.

Audio header sounds (doh) like made for stereo-SID. (provided the address and data bus is available there too)

I suppose a generic sketch where chips and connectors are can enable further insights. The pictures are somewhat blurry which I presume is because of video encoding.


On 12/29/2022 at 9:49 AM, JimmyDansbo said:




Obviously, bodge wires from Prototype#3 are now gone



How can they remove such an important feature? ?


Dev board updates from Kevin Williams

Posted: Thu Dec 29, 2022 1:24 pm
by Edmond D


On 12/29/2022 at 3:23 AM, neutrino said:




What happened to the external-MCU-for-PS/2 ?



I believe it's still there as the shot showing the activity LED up close show a silkscreen marking with the text "System Microcontroller." Another board marking describes how to set J3 for programming the microcontroller.  


Dev board updates from Kevin Williams

Posted: Thu Dec 29, 2022 5:14 pm
by BruceMcF


On 12/29/2022 at 6:23 AM, neutrino said:




... An extra 6522 for userport.. maybe can enable burst transfers? What happened to the external-MCU-for-PS/2 ?



... Audio header sounds (doh) like made for stereo-SID. (provided the address and data bus is available there too) ...



The "extra" 6522 is the VIA#2 that was already there, now become an optional feature.

The video said it was covering "notable changes" ... since it didn't mention the MCU, presumably that is still there, since taking it out would be "a notable change".

The audio header is to allow the internal mixer to be bypassed if people wish to mix externally, so it is the various audio outputs broken out, if the jumper pads are cut.

The slot seems to have left and right audio outputs to go to the internal mixer (or through the audio header if the user prefers) and the slots have IO slot selects and address/data, so it seems all that would be needed for a SID card would be a RDY line clock slowdown circuit.