Commander X16

On 11/3/2021 at 8:16 AM, BruceMcF said:

Yes, although if it is on CS alone, it in any event requires a countdown from /CS to A0-A4 assured valid, and so that countdown requiring /CS at each tick would cover that.



However, it is simpler to .AND. CS & PHI2, since address lines are valid throughout /PHI2. It might be faster if CS and PHI2 are driven through the transceiver and then the AND takes place inside Vera, but it is more parsimonious of pins to AND CS and PHI2 externally and drive that /VeraSEL through the transceiver.  And a single /VeraSEL is more flexible in interfacing to a variety of buses.

The 3-to-8 demux (CD74ACT138E) generating the IO CS signals internally ANDs 3 pins (G1, /G2A, /G2B):



The AND operation of CS and PHI2 could happen implicitly if G1 was connected to PHI2. That said, this would make the timing issue worse since that would mean CS would arrive 12ns after PHI2. I think that to avoid this the best option would be as you suggest - allow CS glitches through and also pass PHI2 through the bus transceiver to the fpga. VERA would then sample A0-A4, CS, RW#, and PHI2 on posedge PHI2.

On 11/3/2021 at 8:16 AM, BruceMcF said:

SD should not be an issue reading in a single clock, since the access to the SPI data port can be organized to be entirely parallel to the Vera pipeline generating the next display row using SPRAM data. The possible contention is when there is a read of port A or port B. If the pipeline is organized to access the SPRAM in alternate clock cycles, then the non-contenting approach is to use the other clock cycle for system bus to SPRAM operations, which may require two Vera internal clocks. If the pipeline is organized to access the SPRAM in every clock cycle and is simply paused when there is a system bus to SPRAM operation, then perhaps the internal read can be accomplished in a single internal Vera cycle.



 

Accessing SPRAM during the same PHI2 clock as the host read is probably a non-starter. The contention with the scanline composer means that you need one cycle to determine whose address goes into SPRAM and the SPRAM IP will respond one cycle after that. Since all VERA addresses are functionally registers, I don't think any operation needs to do this. VRAM reads require the address to be pre-configured, so there is time to fetch the memory and have it waiting in DATA0/DATA1.

On 11/3/2021 at 12:57 PM, Wavicle said:

.. VRAM reads require the address to be pre-configured, so there is time to fetch the memory and have it waiting in DATA0/DATA1.

Yes, the functional equivalent to a write to a latch that is then written at a stage of the rowbuffer generation pipeline that is not reading SPRAM would be a "ready to be read" latched pre-fetch for Port A or B within a given number of Vera cycles of any previous access to the same port (and at reset). That would lead to a lot of unused reads, but it would work, and it would be straightforward to program into the pipeline cycle ... when the "bus access" phase comes up, if a buffered write is waiting, write, if no buffered write is waiting and a pre-fetch read latch has expired, read.