What is the Commander X8?

[xanthrou]

So Commander X8 would probably be/have been a low-cost alternative to X16?

[Perifractic]

So Commander X8 would probably be/have been a low-cost alternative to X16?

You could say that, but then again that’s the goal of the X16E (phase 3) and David’s goal from the start. Hence why the X8 isn’t a thing… Perifractic, X16 Visual Designerhttp://youtube.com/perifractic

[xanthrou]

Just now, Perifractic said:

You could say that, but then again that’s the goal of the X16E (phase 3) and David’s goal from the start. Hence why the X8 isn’t a thing at the moment.





Perifractic, X16 Visual Designer

http://youtube.com/perifractic

I think it would be fair to wait for X16 Phase 3 to discuss about as the original X16 (the very hackable, Phase 1) isn't even out the time I wrote this comment.

[Wavicle]

On 3/3/2021 at 1:09 PM, TomXP411 said:

I'm still holding out for a MiSTer core.  ?  



 

This brings up a question I've had about the X16e since reading about it: what would it have that isn't already in the DE-10 Nano? If the X16e has the physical hardware ports (PS/2, IEC), that would be something, however it seems like those could be implemented far more cheaply as a daughterboard for the DE-10 Nano. Given that other than Vera there are freely available Verilog models for all other hardware used in the X16, it would be reasonable to expect that a Mister X16 core will show up soon after the phase 1 design is finalized.

[BruceMcF]

On 3/7/2021 at 4:58 AM, Wavicle said:

This brings up a question I've had about the X16e since reading about it: what would it have that isn't already in the DE-10 Nano?

Are you referring to the CX16p. CX16c or CX16e?

The CX16p would have an actual 8bit processor, all ASIC through pin chips on the board. The CX16c, though we haven't seen a prototype yet, would have similar, except mostly surface mount and possibly a CPLD replacing the glue logic, and the VERA circuit on the board.

[+] If you don't see the appeal of that, this implies you aren't in the target audience for those. That's normal: nothing is attractive to everybody.

The CX16e, though we are even further from seeing a prototype, would give the ability to run much of the same software that can run on the CX16p (unless it requires the undefined whatevers that can't make the transition to FPGA), without forcing someone to muck about with something like a Mister system.

Ditto [+]

If the software ecosystem around the CX16 is attractive enough to make it worthwhile to develop a Mister simulator for it and for a reasonably large number of people to use that simulator, it would be due in part to the stable development target implied by the system reference design. Without the CX16p existing, there isn't the stable development target which might (bearing in mind that little in life is guaranteed) be the kernel for an attractive retro kind of software ecosystem, for chameleon systems to benefit from by simulating.

Bear in mind the genesis of the CX16 project is people asking The 8bit Guy for advice on what 8bit system to buy if they wanted to have some experience with that style of system, and his realization that there wasn't a classical system that he could recommend without reservation. It's not likely there is a lot of overlap between that core target audience and the typical Mister owner.

[Wavicle]

9 hours ago, BruceMcF said:

Are you referring to the CX16p. CX16c or CX16e?



The CX16p would have an actual 8bit processor, all ASIC through pin chips on the board. The CX16c, though we haven't seen a prototype yet, would have similar, except mostly surface mount and possibly a CPLD replacing the glue logic, and the VERA circuit on the board.



[+] If you don't see the appeal of that, this implies you aren't in the target audience for those. That's normal: nothing is attractive to everybody.



The CX16e, though we are even further from seeing a prototype, would give the ability to run much of the same software that can run on the CX16p (unless it requires the undefined whatevers that can't make the transition to FPGA), without forcing someone to muck about with something like a Mister system.



Ditto [+]



If the software ecosystem around the CX16 is attractive enough to make it worthwhile to develop a Mister simulator for it and for a reasonably large number of people to use that simulator, it would be due in part to the stable development target implied by the system reference design. Without the CX16p existing, there isn't the stable development target which might (bearing in mind that little in life is guaranteed) be the kernel for an attractive retro kind of software ecosystem, for chameleon systems to benefit from by simulating.



Bear in mind the genesis of the CX16 project is people asking The 8bit Guy for advice on what 8bit system to buy if they wanted to have some experience with that style of system, and his realization that there wasn't a classical system that he could recommend without reservation. It's not likely there is a lot of overlap between that core target audience and the typical Mister owner.

I said "X16e"; I'm not sure how that created confusion about which specific device I was referring to. Also, the most complex functionality of the CX16p is on Vera which is neither an ASIC nor a through-hole dip chip. I'm utterly confused about your CPLD comment: the CX16's glue logic should be replaced with an SPLD or EEPLD; and I am not aware of any CPLD on the market which could hope to replace an iCE40UP FPGA.



Have you ever mucked about with a Mister? "Forcing" makes it sound like much more of a chore than my real life experience suggests. "Worthwhile" seems to imply that a developing a CX16 Mister core would be a substantial amount of work. All of the Verilog except VERA would amount to a couple lazy summer weekends by a grad a student with nothing better to do.

That is why my specific question is what would the X16e provide that a DE-10 nano with an IO daughterboard could not. The only example I can glean from your response is "not having to muck with Mister" which is non-sensical. Mister is the most popular environment for the DE-10 nano, but it is not required nor was it even intended when Terasic made the device.  It seems to me that implementing the CX16e on a DE-10 nano would make more sense than developing a new FPGA platform design and also more sense for phase 2 of the CX16.

[BruceMcF]

4 hours ago, Wavicle said:

[1] I said "X16e"; I'm not sure how that created confusion about which specific device I was referring to. ...



[2] Have you ever mucked about with a Mister? "Forcing" makes it sound like much more of a chore than my real life experience suggests. "Worthwhile" seems to imply that a developing a CX16 Mister core would be a substantial amount of work. All of the Verilog except VERA would amount to a couple lazy summer weekends by a grad a student with nothing better to do.



[3] That is why my specific question is what would the X16e provide that a DE-10 nano with an IO daughterboard could not. The only example I can glean from your response is "not having to muck with Mister" which is non-sensical. Mister is the most popular environment for the DE-10 nano, but it is not required nor was it even intended when Terasic made the device.  It seems to me that implementing the CX16e on a DE-10 nano would make more sense than developing a new FPGA platform design and also more sense for phase 2 of the CX16.

[1] Sorry, I didn't catch that when I read it the first time.

[2] But does your real life experience include having an interest in learning how to work with FPGAs, or is it the experience of learning how to work with a DE-10 nano as a chore to be got through in order to get to the part you are interested in? If it's the former, you wouldn't actually have had the experience of what climbing that learning curve is like for the latter.

[3] Your question wasn't why a new FPGA platform design makes more sense, it was what the CX16e would provide that a DE-10 with an IO daughterboard could not.

Obviously the DE-10 nano would have a higher retail price for delivering a complete system to the market, and the new FPGA design would have a lower price, so since the design target for "Phase 3" is to deliver a complete system at a lower price, the DE-10 nano approach could have been ruled out quite early.

Also it makes absolutely no sense for Phase2 of the project, which is targeting the segment of the audience who would like to have all of that lovely through hole ASIC on the board but can't justify the substantial cost of that kind of system, because rather than delivering as close to that as they can get at a lower cost price (and the reduction in board build price is not the only cost reduction, because the smaller board seems likely to be put into a smaller and less expensive case to form the complete system, which will then be less expensive to ship), it delivers almost as far from that as they can get short of just running the CX16 emulator on a PC.

[Wavicle]

30 minutes ago, BruceMcF said:

[1] Sorry, I didn't catch that when I read it the first time.



[2] But does your real life experience include having an interest in learning how to work with FPGAs, or is it the experience of learning how to work with a DE-10 nano as a chore to be got through in order to get to the part you are interested in? If it's the former, you wouldn't actually have had the experience of what climbing that learning curve is like for the latter.



[3] Your question wasn't why a new FPGA platform design makes more sense, it was 1what the CX16e would provide that a DE-10 with an IO daughterboard could not.



Obviously the DE-10 nano would have a higher retail price for delivering a complete system to the market, and the new FPGA design would have a lower price, so since the design target for "Phase 3" is to deliver a complete system at a lower price, the DE-10 nano approach could have been ruled out quite early.



Also it makes absolutely no sense for Phase2 of the project, which is targeting the segment of the audience who would like to have all of that lovely through hole ASIC on the board but can't justify the substantial cost of that kind of system, because rather than delivering as close to that as they can get at a lower cost price (and the reduction in board build price is not the only cost reduction, because the smaller board seems likely to be put into a smaller and less expensive case to form the complete system, which will then be less expensive to ship), it delivers almost as far from that as they can get short of just running the CX16 emulator on a PC.

[2] If you only want to use the Mister+DE-10 Nano platform as a hardware emulation system, all you need to do is write a disk image to an SD card, insert the card, and turn the device on. It's all automated from there. What is the learning curve for running Win32 Disk Imager like, exactly? It sounds like you have no idea what working with the platform is like and have made a lot of incorrect assumptions.

[3] Yes, I know. Why are you stating what my question wasn't? I didn't change the question.

The DE-10 Nano is $135, which is more than the $100 target; and an IO daughterboard, if necessary, would be on top of that. What it gets you now is time to market. If the additional IO ports are not needed or the existing Mister IO board is adequate, the CX16e on DE-10 Nano can be ready to ship, albeit without a case, a week or two after the CX16 architecture is finalized and people can start using it before the first CX16p is out the door. It would be targeted at the same market segment as those who would be interested in the CX16e. Hence the way I stated my question.

[BruceMcF]

4 hours ago, Wavicle said:

[3] Yes, I know. Why are you stating what my question wasn't? I didn't change the question.



The DE-10 Nano is $135, which is more than the $100 target; and an IO daughterboard, if necessary, would be on top of that. What it gets you now is time to market. If the additional IO ports are not needed or the existing Mister IO board is adequate, the CX16e on DE-10 Nano can be ready to ship, albeit without a case, a week or two after the CX16 architecture is finalized and people can start using it before the first CX16p is out the door. It would be targeted at the same market segment as those who would be interested in the CX16e. Hence the way I stated my question.

The question of what the third phase gives that a DE-10 Nano cannot is a different issue than, quoting you, "It seems to me that implementing the CX16e on a DE-10 nano would make more sense". The implied question, "why wouldn't implementing the CX16e on a DE nano make more sense than a dedicated CX16e board built around an FPGA" is a quite distinct question.

Now it's "ready to ship, albeit without a case" beating the CX16p to market for no particular benefit to the project, but at the same time, "targeted at the same market segment as those who would be interested in the CX16e", who are people interested in a system in a case, although happy (or willing) to accept an FPGA board inside the case if it gets the system price down as low as possible.

It seems like you are equating the entire market for Phase3 with the entire audience for a CX16 core on a DE-10 Nano by assumption. Those are not automatically the same groups, even if there may be some degree of overlap.

How big the market for the third phase might be would be an open question, but whether or not it is enough to support that phase of the project is something that is answered by putting it out to crowdfunding.

It's also an open question whether there is a actual market for a CX16 core for a DE-10 Nano, or whether its like a lot of the "retro gaming" crowd that is happy to put all of their money into hardware because they rip off all of their software from pirate bay sites.

[Wavicle]

1 hour ago, BruceMcF said:

The question of what the third phase gives that a DE-10 Nano cannot is a different issue than, quoting you, "It seems to me that implementing the CX16e on a DE-10 nano would make more sense". The implied question, "why wouldn't implementing the CX16e on a DE nano make more sense than a dedicated CX16e board built around an FPGA" is a quite distinct question.



Now it's "ready to ship, albeit without a case" beating the CX16p to market for no particular benefit to the project, but at the same time, "targeted at the same market segment as those who would be interested in the CX16e", who are people interested in a system in a case, although happy (or willing) to accept an FPGA board inside the case if it gets the system price down as low as possible.



It seems like you are equating the entire market for Phase3 with the entire audience for a CX16 core on a DE-10 Nano by assumption. Those are not automatically the same groups, even if there may be some degree of overlap.



How big the market for the third phase might be would be an open question, but whether or not it is enough to support that phase of the project is something that is answered by putting it out to crowdfunding.



It's also an open question whether there is a actual market for a CX16 core for a DE-10 Nano, or whether its like a lot of the "retro gaming" crowd that is happy to put all of their money into hardware because they rip off all of their software from pirate bay sites.

I don't know what it is about leveraging an existing FPGA platform that merits this sort of reaction, but this has become uncivil and I don't care to continue.