Robinkle wrote: ↑Tue Apr 04, 2023 8:25 pm
BruceRMcF wrote: ↑Tue Apr 04, 2023 2:13 pm
Robinkle wrote: ↑Tue Apr 04, 2023 1:20 pm I've also heard it's true. But FPGA's comes in many sizes.
That's why Vera exists ... because an FPGA maker decided to put a 1Mbit RAM module into a commodity FPGA, so it could be done without requiring an FPGA with enough pins for an external Video RAM. That combination of an unusually large RAM component for an FPGA of that size -- and therefore relatively low cost -- is the foundation of the Vera design. Given that, it's not surprising that Vera is fully committed for I/O pins with a large majority of logic resources also committed.
Sure can be. I haven't looked into which FPGA that is used, nor it's alternatives. Often FPGA's even come in difference capacities with the same footprint.
Yes. IIUC, the one the Vera is implemented in has an unusually large PSRAM module for such a modest logic capacity (and modestly priced) commodity FPGA.
BruceRMcF wrote: ↑Tue Apr 04, 2023 2:13 pm
But the Vera board is already designed for the FPGA that the Vera is implemented on. As the video points out, it's already too late for design suggestions that involve scrapping the board design and starting over from scratch.
If I remember correctly, that was about using a Z80 on the X16. The vera chip is on a small daughter board, which also will be designed with IMDH port. So I guess it's not that late in it's design phase.
I reckon if you listen closely, that response is not narrowly focused on the "why not switch to a Z80?" question alone, but is directed more broadly to sweeping changes.
BruceRMcF wrote: ↑Tue Apr 04, 2023 2:13 pm They could indeed do a look around to see whether there is a suitable FPGA with an embedded 1Mbit RAM (in some form) for handing the Vera model, and also the FM core, and also the work done by much of the glue logic, and enough I/O pins to handle all of those roles, for the X16c board, which is more in the "early design" phase than the "final shakedown to determine if there are any tweaks required before proceeding to our first main release" phase.
That's all I'm saying.
If you are
only talking about the "2nd Gen", aka X16c, that's different. From the outside, it seems like the really serious start of the X16c design process is when the X16 Dev Board design is locked down, so they may well be in the preliminary stage now when different options can be batted about.
BruceRMcF wrote: ↑Tue Apr 04, 2023 2:13 pm But the X16 Dev board is in the final shakedown phase, and a change as major as upgrading to an entirely new FPGA, quite possibly in another FPGA family, seems like a bit beyond a final tweak.
The VERA board can be made compatible with the X16 Dev board with any FPGA, the FPGA just has to be configured to function the same way with the same code. That's the beauty of FPGA's.
But the Vera daughter-board doesn't presently
handle the YM2151 functions, so it's chip select is not presently designed to trigger when the YM2151 is being written. And since the daughter-board block pin headers are directly designed for the daughter-board, and Vera is totally pin-constrained, there aren't likely to be any spare pins going into the daughter-board where they can solder in a bodge wire from the YM2151 chip select trace. Also, the pins don't exist to carry the digital information to the DAC for the OPM chip.
And of course, the YM chip is the only one with proper hardware envelope control. If the solo instrument gets four channel polyphony, and the background instruments two, you can still have three distinct FM instruments simultaneously, and with the low frequency oscillator you can have either volume or pitch vibrato on one of the channels.
Though I do see the cost issue. I wonder what would better. Using an FPGA replacement board for the FM chip. Or implement it on the VERA using a bigger FPGA?
But the Vera board
plugs into the main board, and it is the main board that hosts the YM2151, and its DAC, and the circuit for accessing the YM2151, and the routine from the YM2151 DAC into the onboard audio mixer. If you are comparing
for the X16 Dev board, then it's better using the FPGA replacement board, because that is the board that is for people who care about having the through hole DIP parts. At least that way, if someone can source an actual YM2151, they can replace it into the socket.
The reliance on an out of production part was never a very promising approach for the X16c, if it is intended to be an open-ended production run with as high a volume as the market will bear. Even if they were not having problem ordering a hundred good new-old YM2151's, they would be well advised not to design the X16c to rely upon that availability.
So the X16C should not be including a separate YM2151 chip in the design. The question for the X16c is rather whether to leave the Vera design alone and look to integrating some or all of the chip select logic into the FPGA containing the YM2151 core, or whether to migrate the Vera, the YM2151 logic, and whatever parts of the chip select logic it makes sense to add into a single, larger FPGA -- probably one with the I/O pins to support the entire address bus, whether in a single pass or in two clock cycle subphases supported by some fast latches.
That design choice rests on information lying far, far outside of the dribs and drabs of hardware knowledge I possess, so all I can do is to point to the fact that those two options may exist.
