Commander X16

Dacobi wrote: ↑Wed Mar 08, 2023 1:14 am One thing I still don't understand. How does VERA know when a new byte is written to data0/1?

The way it usually works on other ICs is, in addition to the address pins and the data pins, there's usually a chip select, a read, and a write pin. While chip select is asserted, each time there's a pulse on the "write" pin, the IC considers that a new write, so for example, if you set the address pins to $1234, the data pins to $56, and pulse the "write" pin 6 times, the IC will see that as $56 being written to address $1234 a total of 6 times (i.e., writing the same value to the same address multiple times).

I believe the VERA works the same way, just based on what I see from a cursory glance, but I don't know the timing specifics, nor how fast it can accept writes before they get dropped.

if you set the address pins to $1234, the data pins to $56, and pulse the "write" pin 6 times, the IC will see that as $56 being written to address $1234 a total of 6 times (i.e., writing the same value to the same address multiple times).

So I guess the 6502 has a "write" pin for writing to memory that gets repurposed by some address logic whenever you run "sta data0"?

Basically, yes - the CPU's data bus is connected to VERA's data bus, and inside of VERA, there are a bunch of logic gates that decide where the bus is connected, based on the value of the address bus.

Honestly, that's a whole college class, and it's way too complex to talk about in this forum post. (It's off topic, for one thing.) If you want to understand address logic in a computer, feel free to start a new thread and ask away. We'll try to answer your questions as best we can.

My question is mostly what a DMA controller would need to do to write/read to/from VERA VRAM? Is the VERA "write" pin exposed on the expansion bus?
(Edit) Or is it simply a question of setting the right address on the address bus?

If the DMA controller is connected to the same bus as the CPU and the VERA, then it would access VERA memory the same way the CPU does.

The way busses work is, there's address lines, data lines, and some kind of read line and write line (varies based on CPU architecture), at minimum. Also in the bus circuitry, there's logic to figure out which component to send a chip select signal to, based on what the current address on the bus is.

So the DMA controller would first need to gain control of the bus (i.e., pull the CPU off of it), then put the address of one of the VERA's data ports onto the bus, put a data byte on the data lines if it's a write, then signal "read" or "write" on the read/write lines. Ideally, the program will have set the VERA's data port to the desired VRAM address first, before triggering the DMA. Then, the DMA just alternates between the VERA address and a RAM address over and over until the desired number of bytes (configured by the program) have been transferred, and then control of the bus is passed back to the CPU, and the program resumes.

Ah, that was the nature of Dacobi's question? Here and I was developing concern whether, when addressed, the VERA will be able to handle reads or writes every other clock cycle, since it relies on the VERA clueing in to the fact that it's being addressed, and the fastest a 65c02 could normally pump data to it is with a stz every 4 cycles. And to be honest, I still don't really know the answer to that, but I'm willing to take the chance and potentially fail anyways just for the educational value of learning some Verilog.

So the DMA controller would first need to gain control of the bus (i.e., pull the CPU off of it), then put the address of one of the VERA's data ports onto the bus, put a data byte on the data lines if it's a write, then signal "read" or "write" on the read/write lines. Ideally, the program will have set the VERA's data port to the desired VRAM address first, before triggering the DMA. Then, the DMA just alternates between the VERA address and a RAM address over and over until the desired number of bytes (configured by the program) have been transferred, and then control of the bus is passed back to the CPU, and the program resumes

I get the general concept, but what are the actual lines that need to be asserted?

The GitHub documentation shows VERA having MEMWE and MEMOE but they are not listed on the expansion slots?

How would a program assert the IO3-7 Select lines?
And then how would the expansion module take the CPU off the bus during transfer?

I think I had a course on Address bus logic, but that was 25 years ago and I never used it since or in practice.

I have worked on circuits with more than one IC so I'm familiar with Chip select, but I've never worked on anything like a whole computer architecture.

Dacobi wrote: ↑Wed Mar 08, 2023 7:02 pm I get the general concept, but what are the actual lines that need to be asserted?

The GitHub documentation shows VERA having MEMWE and MEMOE but they are not listed on the expansion slots?

How would a program assert the IO3-7 Select lines?
And then how would the expansion module take the CPU off the bus during transfer?

I think I had a course on Address bus logic, but that was 25 years ago and I never used it since or in practice.

I have worked on circuits with more than one IC so I'm familiar with Chip select, but I've never worked on anything like a whole computer architecture.

I think the point is that we don't have to worry about MEMWE and MEMOE, or the various other pins. Logic on the board is already looking at the address bus, seeing "some address in the range $9F20-$9F3F", and when that happens it triggers the IO as appropriate. And we appear to have the same lines to the address and data bus as the CPU, including the RWB line for signalling reads and writes.

We also have the RDY line, which I believe is how we'd kick the 65C02 off of the bus:

So the program will write the addresses and the byte count to the registers somewhere in $9F20-$9F3F
The module then halt CPU by pulling RDY low and then reads/writes bytes at the specified addresses by toggling RWB?

Dacobi wrote: ↑Wed Mar 08, 2023 8:19 pm So the program will write the addresses and the byte count to the registers somewhere in $9F20-$9F3F
The module then halt CPU by pulling RDY low and then reads/writes bytes at the specified addresses by toggling RWB?

Let me rephrase:

We don't have to worry about MEMWE and MEMOE to or from the VERA daughterboard, or the various other pins it communicates through. Logic on the mainboard is already looking at the address bus, seeing "some address in the range $9F20-$9F3F", and when that happens it triggers the VERA pins as appropriate to read or write. And expansion cards appear to have the same lines to the address and data bus as the CPU, including the RWB line for signaling reads and writes, so if the controller is told to write to a VERA address, then we should be able to handle it just like the CPU does, by placing an address on the address bus and asserting or deasserting the RWB line appropriately.

My plan, at least, was not to add DMA to the VERA itself -- the VERA is well too complicated for my nascent understanding of Verilog. And if RDY doesn't allow another device to use the bus (such as the CPU leaving its address/data lines set based on whatever it was last doing), then my plan is toast anyways.