1 hour ago, jbaum81 said:
Nope, I cooked the Oscillator ? , I must have hooked something up backwards, Ordered a new 8mhz oscillator and it's fine.
Also figured out the issue with the flipflops on the banks. I was sending the clock signal to the flipflops when the address was set and clock went high, but for some reason the datelines were not ready fast enough, which doesn't seem consistent with 65c02 data sheet?!? ...
Now THAT seems like it makes sense, even to a software hand ... if it happened to be an HCMOS crystal oscillator circuit in the can, fry the inverters, which are the source of the VCC input, and seeing the crystal oscillation instead of a square wave seems likely, since the inverters are what squares up the wave.
But anyway, that's second timing is what the August 2018 datasheet says on page 26 ... the fourth line in the timing chart is the write data ... it begins with the data written the previous cycle, which should be valid tDHW after the start of the new cycle with the PHI2=0 transition ... it then crosses over since it is indeterminate until it crosses over again tMDS after the PHI2=1 transition for the rising clock cycle. So the valid write data is from tMDS (max 25ns[+]) after the rising clock cycle until tDHW (min 10ns) after the falling clock cycle. With a glue logic latch, data can be latched on the fall of the clock after the part is selected, as long as the latch is effective within 10ns of the falling clock.
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[+ At +5VCC, 40ns at +3.0/3.3VCC, 70ns at +2.8VCC, 140ns at +1.8VCC.]