14 minutes ago, Lorin Millsap said:
You are basing that on obsolete information. The X16 uses addresses $00 and $01 for banking control freeing up the VIA for better uses.
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The C64 uses a PLA, is the CX16 using programable logic?
With the removal of other devices out of the IO area why not just stick a couple D Flip-flops there? Hell, you wouldn't even have to sacrifice any of the expansion banks, you could stick them right next to the VIA's since they don't use all of their address space. Seems to me it would be a hell of a lot easier to divide the space allotted to the VIA's considering the majority of the logic is already there for that, rather than dividing up low ram address space. What is being gained by this? It certainly can't be just for the one measly clock cycle gained for ZP when bank switching.
@ 8mhz the clock cycle is 125 ns, 30ns for address setup time and it appears data is latched in on the falling edge of the cycle leaving 95ns for read. As far as I can tell Ram and Rom are going to be the slowest devices on the Bus. Wouldn't it be more advantageous to try to reduce propagation time and see if you could get a couple more mhz out of the clock? @10mhz you have 70ns after address setup in the clock cycle, not enough to write out on the rising edge of the clock, but the ram I found is 55ns from address valid, that's more than enough time to bring enable and write down with the address and not use the clock, no? I'm pretty sure there are SMD ROM's that can match that performance and adapters are available to adapt between smd and dip.
I don't know, I'm just thinking aloud here having fun going through this stuff. I'm curious to know the reasoning behind the design decisions, I'd like to learn something.