17 minutes ago, lamb-duh said:
hardware can't directly access ram because only one address can be read from ram at a time, and the 6502 does a memory read or write nearly every cycle. so, communication with hardware needs to be done with latches that are (physically) outside the main ram.
That's not quite correct, but Cyber's not correct, either.
Hardware actually CAN directly access RAM. It just needs to assert the DMA pin on the CPU. This suspends the CPU and lets the hardware access the bus.
However, that's not how I/O devices usually do it. They use something called the Chip Select (CS) pin.
Every clock cycle, every device on the bus looks at the CS pin and decides whether or not it should respond to the address and data bus. If the CS for that device is high, that device is allowed to talk to the bus. If the CS is low, that device is NOT allowed to talk to the bus.
On the Commodore 64, the device that controls the CS pin is the PLA chip. This chip examines the data bus address on every clock cycle, then sets the CS pin for every device on the system based on the current bank configuration and address on the bus.
So when the address is in the RAM range, the PLA sets the CS pin tied to the RAM chips. When the address is in the ROM range, the CS pin for the ROM is activated. This is what allows RAM, RAM, and I/O to all live in the same address ranges and be banked in and out as needed by the operating system.