Splitting clock signal - 6502

Bader · Post by **Bader** » Fri Oct 16, 2020 11:59 am

Hello

Just got a 6502 A in the mail which I understand runs at 2MHz. I don't have any of those crystal oscillators, but I do have a 4MHz. Can I split the signal using logic gates? At the top of my head perhaps an XOR gate and a ~~D-latch~~ set/reset latch should do it? But the details are not the point, the question is, is it viable or would it not be exact enough?

Thanks

StephenHorn · Post by **StephenHorn** » Fri Oct 16, 2020 3:30 pm

I don't have time to find the exact location of his solution, but didn't Ben Eater do some kind of clock division for his homebrew VGA circuit?

Bader · Post by **Bader** » Fri Oct 16, 2020 3:59 pm

oh I'll have a look, thanks ?

EMwhite · Post by **EMwhite** » Fri Oct 16, 2020 5:24 pm

There is also this:

He is no Ben Eater (not quite as organized, rehearsed, etc.) but based on his clock starting point, he appears to have based his design on Ben's original clock. I've got clock dividers in my modular synthesizer that work in very much the same manner. The shape of the signal (that the presenter struggles with) ultimately causes issues with the ICs dependent on clock but I think below a given # of single digit Mhz. you are probably ok and will need to try it.

Bader · Post by **Bader** » Fri Oct 16, 2020 7:47 pm

Been playing around in Logisim. To halve the frequency, don't I really just need a D-latch with the invertered Q going to the enable (or is it called input) pin? Like I've done in the picture? I don't really need to split the signal, just remove half the ticks.

StephenHorn · Post by **StephenHorn** » Fri Oct 16, 2020 9:52 pm

Seems like that would work, sure.

Bader · Post by **Bader** » Sat Oct 17, 2020 3:36 pm

awesome, thanks all!

Bader · Post by **Bader** » Sat Nov 07, 2020 6:33 pm

update, if anyone is curious ?

Not getting it to work. I've come as far as making the outputs do as I want as long as I don't use not Q as input. When I do use not Q then switchover seems random. My guess is I have to de-bounce it but I really have no idea. Will continue experimenting when I'm closer to sobriety ?

StephenHorn · Post by **StephenHorn** » Sun Nov 08, 2020 12:39 am

6 hours ago, Bader said:

update, if anyone is curious ?

Not getting it to work. I've come as far as making the outputs do as I want as long as I don't use not Q as input. When I do use not Q then switchover seems random. My guess is I have to de-bounce it but I really have no idea. Will continue experimenting when I'm closer to sobriety ?

Not to ask silly questions, but is there a timing graph for the component you're using, and do you know whether your clock input is conforming to the latch's requirements?

JimmyDansbo · Post by **JimmyDansbo** » Sun Nov 08, 2020 7:24 am

In theory, it should work. I have just tested in Logisim as well, both the buil-in d-latch and one made from NAND gates seems to be able to divide the clock signal.

As StephenHorn says, ensure that your chip(s) can handle the signal they receive. (dig in to the datasheets).