Change STA $9F24 to STZ $9F24, because according to the FX documentation, when cache-write mode is enabled, the value you write to DATA0 or DATA1 acts as a nybble-mask which determines which nybbles of the cache get written out to VRAM, where a 0 bit writes the nybble and a 1 bit masks it out.Ed Minchau wrote: ↑Wed Aug 30, 2023 6:39 amCode: Select all
lda #$04 ;DCSEL = 2 sta $9f25 lda #$40 ;enable cache write, addr-1 mode normal sta $9f29 lda #$10 ;multiply sta $9f2c sta $9f24 ;send result to VRAM stz $9f29 ;disable cache write stz $9f25 ;DCSEL = 0
I suspect this may resolve the issue in your second post too.