1 interrupt / NMI is being serviced, (latch is clear, $0001 is old value) ISR has read $0001.Wavicle wrote: ↑Wed Jun 28, 2023 8:07 pmI'm the one that proposed using the VPB signal as an additional reset to the ROM bank latch and I looked at it fairly closely. Ultimately the decision was VPB as the only signal, which I disagree with but that's because I'd like an advanced debugger to insert itself after reset but before the CPU starts executing anything in a known state. For all other situations, VPB is adequate. VPB is always asserted on the negative phase of the first cycle of a vector pull. VPB does not glitch during non-vector pull operations and ISR does not initiate a vector pull hence I'm not sure what the concern is.spargue wrote: ↑Wed Jun 28, 2023 12:41 pm From what's been made public of the design and the VPB latch mod I'm not sure if NMI can be accounted for without some HW rework of the main system. Ultimately several design choices have crippled some novel implementations of expansion and you have to do everything the slow way without any form of modern acceleration. I'm not really sure the VPB latch mod is 100% sound as it would change the latch before exiting the ISR. So ISR has to exit from a ram instruction rather than a form a ROM instruction.
2 card begins bus access, (ISR hasn't gotten to write $0001 to 0 yet)
3 card does Read $0001 (exchanges data then restore $0001)
4 latch is now value before entering ISR (not bank 0), but ISR is still running assuming it's bank 0.
This creates hazards.
Since only 1 card can get bus access at a time, you might as well get the CPU to set the banks needed in the service routine as the CPU has to be the arbiter. No point in getting a card to do its own advanced bus master it just adds complexity to the card.