Will YMF825 (SD-1) be the ultimate answer to YM2151 (and maybe ymf262)shortage?

[GTR3QQ]

Some dying memory just came back about an amazing chip which still in production by YAMAHA - the mighty YMF825 (a.k.a SD 1)
It is feature compatible (with minor details difference) to YMF262, just need to translate the register.
A translator had already been built.
https://github.com/danielrfry/opl2sd1
And a vid demo ing this.
https://m.youtube.com/watch?v=BEgAx0jngKQ
And it sounds wholesome!!!!

If you're going with the duel opl3 sound card eventually, why not take it a step further and make it duel SD 1 instead?
You can *hit three birds with one stone.

a. No more worring for using old chips(like high price, unavail, partially faulty, counterfeit chips) Which fits CX16 original idea of using modern parts.
b. 22cent per chip and no need to use dac or amp even. (you might get better price buying bulk, shipping not included)
c. Remain *compatible whilst still have more capabilities than Convenienlal OPL3 (4 op per channel, *16 total, 29 waveform, using two chips for stereo means you can have 32 4op channel, staggering!)
Giving CX16 the possibility of becoming an absolute FM powerhouse!!!

Making it absolutely standings out in audio department.
I don't even know what amazing possibilities there is. I and many others would like to know the answer.



It is proven compatible (kiada) to OPL family. Maybe even The OPM family as well(although the algorithm connects OPs differently, but at least it is proven OPL "compatible")

Some facts listed on the datasheet
Features
□ 16-voice polyphonic FM synthesizer
□ 29 on-chip operator-waveforms and 8 algorithms offers a whole variety of
sound
□ Synchronous serial data link for host controller interface
□ Integrated loudspeaker driver (Also supports external amplifier connection)
□ Integrated 3-band equalizer
□ Integrated 16-bit monaural DAC
□ Integrated power-on reset
□ Flexible Power Supply Configurations

Sure, only 16 channels,and mono, but if you do go with duel chip you can solve the stereo problem, don't know if it is possible with a clever amp design, make The chip do 32 mono fm goodness.
Or just put 2 more chips on, then a jaw- dropping 64 polyphonic can achieve. And no more 18 > 16 problem.
Even if you just using 2 chips, you can still getting pretty good opl3 compatibility by cutting off low volume channels,proven to work by the video above ,difference is very hard to notice.


Hardware design is a taunting task through. Just with my limited knowledge, i can think of a couple hard to solve.
a. syncing the two chips.
b. is there enough cpu power to do this? if not, a dedicated APU or some kind of CPLD?
c. how to talk to the rest of the system? it runs on serial (I2C ?), so more CPLDs or 75 glues.

Let alone the software side of things. through proven but is on a Quantum computer compare to 65c02 with 8 mhz.


Just imagine, 32 polyphonic 4op FM, you can only found this combo in CX16. unicorn!!!
How big this can give the CX16 an edge when launch???


"The best sound system you can find in the whole 8 bit computer class."



It will really hit the chip tune composing creators hard.
And to end user it means excellent sound for 1 8th of The price if go with duel opl3 and/or FPGA YM2151.
Heck , with it only be SSOP24 package, I bet it is possible to design a pcb that will fit in the YM2151 DIP 24 socket, don't even need a card.
Yes it breaks compatibility with software Witten for ym2151, but assuming you do want to use duel opl3 regardless, why not??


To summarise, if hardware/software challenges could be solved in time for launch, even after launch, this would give CX16 its unique point like VERA and insensitive every one to buy one.

[TomXP411]

No one has been able to find this at the distribution level.

Do you have a contact at Yamaha who would be able to sell 100 units now and something like 100-1000/year after that? If so, I'm sure the team would love to talk to them.

As you say - if we're going to switch, now is the time.

[BruceRMcF]

From the data sheet I saw, it uses an Mode0 SPI bus, so with a VIA and an quad 2-input NAND gate you can get a reasonably fast -- faster than original I2C -- data transfer. But since it has a timed FIFO queue for control events, a bit banged SPI might suffice, in which case there are already sufficient lines available on the System VIA#1.

As TomXP411 points out, the first question is whether there is an actual amount to be purchased at the volume the project needs. The challenge is that the chip is mainly aimed at Chinese producers, so someone who residing in the Shenzhen who speaks Chinese would be the most likely to be able to track down a supply.

[TomXP411]

Ewww. No. SPi consumes too much CPU time to be useful.

It might be possible to fake SPI using the bit shifters and the handshake clock, but that just increases the complexity level for programmers. At this point, I'm thinking an RP2040 or FPGA is a better choice.

[GTR3QQ]

From the data sheet I saw, it uses an Mode0 SPI bus, so with a VIA and an quad 2-input NAND gate you can get a reasonably fast -- faster than original I2C -- data transfer. But since it has a timed FIFO queue for control events, a bit banged SPI might suffice, in which case there are already sufficient lines available on the System VIA#1.

As TomXP411 points out, the first question is whether there is an actual amount to be purchased at the volume the project needs. The challenge is that the chip is mainly aimed at Chinese producers, so someone who residing in the Shenzhen who speaks Chinese would be the most likely to be able to track down a supply.

I might know a guy who knows a gal in JangXi, China. A quote maybe see if he can get.
So long as you're certain the hardware/software is possibly compatible.

[GTR3QQ]

No one has been able to find this at the distribution level.

Do you have a contact at Yamaha who would be able to sell 100 units now and something like 100-1000/year after that? If so, I'm sure the team would love to talk to them.

As you say - if we're going to switch, now is the time.

as posted above, supplies need a ask around. but from what is listed on aliexpress, chances are high though. But I won't bet on him, maybe contact seller from aliexpress is better since they already listed as such 22cents per chip without shipping.
What about level-shifting? if use VIA it is TTL after all.
And cost, assuming 22cents for it , 2 will be 44cents, how much supporting logic/passive you think is need?

[BruceRMcF]

From the data sheet I saw, it uses an Mode0 SPI bus, so with a VIA and an quad 2-input NAND gate you can get a reasonably fast -- faster than original I2C -- data transfer. But since it has a timed FIFO queue for control events, a bit banged SPI might suffice, in which case there are already sufficient lines available on the System VIA#1.

As TomXP411 points out, the first question is whether there is an actual amount to be purchased at the volume the project needs. The challenge is that the chip is mainly aimed at Chinese producers, so someone who residing in the Shenzhen who speaks Chinese would be the most likely to be able to track down a supply.

I might know a guy who knows a gal in JangXi, China. A quote maybe see if he can get.
So long as you're certain the hardware/software is possibly compatible.

It's not a through hole package, but the datasheet is explicit that it is Mode0 SPI (that is, SHOW rather than TELL, it shows the 4 wire serial interface timing diagram, and you can see the serial clock idling low, latching data on the rise,and data transitioning on the fall).

Jumper J4 brings out the extra VIA#1 pins:

CA1  Pin1 - Pin2  CA2
PB0  Pin3 - Pin4  PB1
PB3  Pin5 - Pin6  CB2

... so you can support an SPI bus with one GPIO as the SCLK line (Pin3), one GPIO as Master-In/Servant-Out (Pin4), one GPIO as Master-Out/Servant-In (Pin5) and a select line. Either CA2 or CB2 can be set as a high or low output, so the J4 jumper is able to support a bit-banged two device SPI bus.

You could change it from general purpose I/O to a dedicated SPI supported by Kernal Device Select and Byte Read/Write, Read, and Write operations, dedicate CB2 to the YMF825 (and not bring it out onto J4) and leave CA2 as an expansion SPI device select. For the current revision of Developer boards, you could put a daughterboard on J4 with a ribbon cable over to the external analog audio mixer pin header J10, to replace the YM2151 outputs with the YMF825 outputs.

For an updated board where the VIA pins used for an SPI bus are directly routed to a YMF825 socket, the YMF825 could be assembled to a breakout board to make it a through-pin equivalent device much more cheaply than the the FPGA doing a hardware emulation of a YM2151, because it is designed to be a +5v tolerant chip (indeed, it requires +5v for it's analog side, and can source the 3v for its digital side either directly from a 3v line or through a 5v->3v circuit built into the chip).

For the "Gen2" X16console board, it would go straight onto the board with the other +5v SMB parts, like the 65C02 and 65C22.

The datasheet says its a mono DAC, but it has two line outs (or speaker outs when driving a speaker directly), so I presume that the mixer can locate it in different locations in the soundscape with the level of the two outputs.

[GTR3QQ]

From the data sheet I saw, it uses an Mode0 SPI bus, so with a VIA and an quad 2-input NAND gate you can get a reasonably fast -- faster than original I2C -- data transfer. But since it has a timed FIFO queue for control events, a bit banged SPI might suffice, in which case there are already sufficient lines available on the System VIA#1.

As TomXP411 points out, the first question is whether there is an actual amount to be purchased at the volume the project needs. The challenge is that the chip is mainly aimed at Chinese producers, so someone who residing in the Shenzhen who speaks Chinese would be the most likely to be able to track down a supply.

I might know a guy who knows a gal in JangXi, China. A quote maybe see if he can get.
So long as you're certain the hardware/software is possibly compatible.

It's not a through hole package, but the datasheet is explicit that it is Mode0 SPI (that is, SHOW rather than TELL, it shows the 4 wire serial interface timing diagram, and you can see the serial clock idling low, latching data on the rise,and data transitioning on the fall).

Jumper J4 brings out the extra VIA#1 pins:

CA1  Pin1 - Pin2  CA2
PB0  Pin3 - Pin4  PB1
PB3  Pin5 - Pin6  CB2

... so you can support an SPI bus with one GPIO as the SCLK line (Pin3), one GPIO as Master-In/Servant-Out (Pin4), one GPIO as Master-Out/Servant-In (Pin5) and a select line. Either CA2 or CB2 can be set as a high or low output, so the J4 jumper is able to support a bit-banged two device SPI bus.

You could change it from general purpose I/O to a dedicated SPI supported by Kernal Device Select and Byte Read/Write, Read, and Write operations, dedicate CB2 to the YMF825 (and not bring it out onto J4) and leave CA2 as an expansion SPI device select. For the current revision of Developer boards, you could put a daughterboard on J4 with a ribbon cable over to the external analog audio mixer pin header J10, to replace the YM2151 outputs with the YMF825 outputs.

For an updated board where the VIA pins used for an SPI bus are directly routed to a YMF825 socket, the YMF825 could be assembled to a breakout board to make it a through-pin equivalent device much more cheaply than the the FPGA doing a hardware emulation of a YM2151, because it is designed to be a +5v tolerant chip (indeed, it requires +5v for it's analog side, and can source the 3v for its digital side either directly from a 3v line or through a 5v->3v circuit built into the chip).

For the "Gen2" X16console board, it would go straight onto the board with the other +5v SMB parts, like the 65C02 and 65C22.

The datasheet says its a mono DAC, but it has two line outs (or speaker outs when driving a speaker directly), so I presume that the mixer can locate it in different locations in the soundscape with the level of the two outputs.

Don't really know if it will do YM2151 well enough, algorithm is different aprantly.
The demo video showed a frame of the YMF825 programing guide which I can't find right now, so no way for me to verify the algorithm problem.
And also, the LFO do not exist (or implemented differently) on OPL(SD 1)family.
Can not know how close it will be if emu. a 2151, without programing guide.

I'm all for PCB adapters to DIP.
SSOP24 isn't that bad soldering by hand. Anything but BGA can solder easily with practice.

[GTR3QQ]

Ewww. No. SPi consumes too much CPU time to be useful.

It might be possible to fake SPI using the bit shifters and the handshake clock, but that just increases the complexity level for programmers. At this point, I'm thinking an RP2040 or FPGA is a better choice.

Hold on? there was a previous attempt to get the chip from Shenzhen? how did it go?

[TomXP411]

Ewww. No. SPi consumes too much CPU time to be useful.

It might be possible to fake SPI using the bit shifters and the handshake clock, but that just increases the complexity level for programmers. At this point, I'm thinking an RP2040 or FPGA is a better choice.

Hold on? there was a previous attempt to get the chip from Shenzhen? how did it go?

I don't think anyone here has attempted to get it from Shenzen. We've all looked at parts suppliers, like Mouser and such. Those chips are not available through any of those distributers.