Can the VERA's FPGA be reprogrammed?

[StinkerB06]

Is it possible to manually (not from software) re-program the VERA's on-board FPGA to perform different kinds of tasks? This can perhaps allow the video modes to be changed, or even allow a virtual 2nd CPU to be created if there's enough spare logic blocks. I might as well replace the default PSG/PCM audio with my own Amiga-like sampler, to be paired with the otherwise hard-coded YM2151 and SAA1099 audio.

I know users will be able to re-program the X16's flash ROM with their own software, to be paired with their custom VHDL/Verilog code if only @Frank van den Hoef makes this possible.

[Kilian Hekhuis]

I think it's in the faq somewhere, but otherwise it was said on Facebook, that this will not be possible.



 

[BruceMcF]

35 minutes ago, StinkerB06 said:

Is it possible to manually (not from software) re-program the VERA's on-board FPGA to perform different kinds of tasks?

Certainly not if they can help it ... one of the design goals is a stable target for programming. A blizzard of individual FPGA hacks and tricks would run directly counter to that design goal. The aim is to make the Vera as much as possible like the custom ASIC video chips of the 8bit machines, and see what people can do within the constraints of the platform.

There already are chameleon systems out there, it would be pretty redundant to be working on making another one.

[Frank van den Hoef]

On the real hardware, there will be a way to reprogram the FPGA image if necessary to fix any bugs that are discovered after release. (This involves putting a jumper on the VERA board to enable access to the flash chip from the CPU.) So yes, if you would like to hack around you can, it is (will be) your hardware. Also the FPGA does have a feature where it can store up to 4 FPGA images in the flash chip, which could be nice for hardware hackers to allow the original image to be present in addition to their own creations.

Do note, that this will not be officially supported and normally users are expected to run original firmware. So if you mess up, it is on you.

[TomXP411]

12 hours ago, BruceMcF said:

Certainly not if they can help it ... one of the design goals is a stable target for programming. A blizzard of individual FPGA hacks and tricks would run directly counter to that design goal. The aim is to make the Vera as much as possible like the custom ASIC video chips of the 8bit machines, and see what people can do within the constraints of the platform.



There already are chameleon systems out there, it would be pretty redundant to be working on making another one.

You can pretty much count on people releasing VERA hacks, almost as soon as the hardware is out there. The only thing that will keep down the number of hacks is the fact that not many people have the knowledge and tools to effectively code for FPGA systems.

 

[picosecond]

7 hours ago, TomXP411 said:

You can pretty much count on people releasing VERA hacks

Some folks (not the ones commenting here) may have the wrong idea about what VERA hacks would look like.  Unless Frank and team release the source HDL, VERA is a blank slate to aspiring FPGA designers.  It's an FPGA development board with VERA-compatible connectors.

It's great that re-imaging is supported. It saves the non-trivial task of rolling your own mechanically and electrically compatible PCB.  But any hacks will be completely new designs, not minor tweaks to the existing VERA.  Depending on which FPGA they have chosen it might even make a nice standalone development board. I'm hoping for Lattice Semi's ice40up5k.

[TomXP411]

15 hours ago, picosecond said:

Some folks (not the ones commenting here) may have the wrong idea about what VERA hacks would look like.  Unless Frank and team release the source HDL, VERA is a blank slate to aspiring FPGA designers.  It's an FPGA development board with VERA-compatible connectors.



It's great that re-imaging is supported. It saves the non-trivial task of rolling your own mechanically and electrically compatible PCB.  But any hacks will be completely new designs, not minor tweaks to the existing VERA.  Depending on which FPGA they have chosen it might even make a nice standalone development board. I'm hoping for Lattice Semi's ice40up5k.

I'm really hoping the source code gets released, because I really want to see Commander on the MiSTer FPGA platform. All of the other components in Commander already exist as open source FPGA code; it's just VERA that is unique, at this point. 

 

[Kilian Hekhuis]

7 hours ago, TomXP411 said:

I'm really hoping the source code gets released, because I really want to see Commander on the MiSTer FPGA platform. All of the other components in Commander already exist as open source FPGA code; it's just VERA that is unique, at this point. 

 

Although I can understand you'd want that, I'm pretty sure this good against the spirit of this project. Many people have poured hundreds of hours in this project, and not just to see their work reimplemented on Mister, without them getting a dime for it.



 

[TomXP411]

11 minutes ago, Kilian Hekhuis said:

Although I can understand you'd want that, I'm pretty sure this good against the spirit of this project. Many people have poured hundreds of hours in this project, and not just to see their work reimplemented on Mister, without them getting a dime for it.

 

Then you don't really understand the motivation behind the project. Why do you think the emulator, the firmware, and all of the documentation are already released under open source licenses? 

 

[Kilian Hekhuis]

Explain then why they didn't go for Mister right away? Also, the "firmware" (I assume you mean the kernal) isn't open source, as it's licensed from Cloanto.