3 hours ago, Wavicle said:
I think playing all the tricks at 8MHz, it comes to around 30ns for combinatorial logic to assert the correct chip select. I guess it is theoretically feasible as long as the address decoding isn't more than 3 gates deep.
I was skimming the AHCT datasheet tonight and another problem occurred to me that I haven't had time to think through in depth: the output drive current of those parts is very weak - 8mA (which is probably why they have lower propagation times, they don't have to switch as much current). That's 1/3 the output current of the ACT parts. I'm not certain that it would be a problem, and I do know for certain that my ability to guesstimate parasitic capacitance sucks, but given the (apparently) long board traces I would be concerned that load capacitance might eat up most of that 30ns of headroom. If the CX16 can run stable at 8MHz, I'm definitely dragging one into work and probing with a fast scope because my intuition is telling me there shouldn't be enough timing margin to do so.
Hence why I can imagine people playing around with trying a mix of them if they are on the edge. So if you have a demux with high output that can be wired-ored and the result fed through an inverter to get to the low select, you might prefer that inverter to be ACT for drive, and the demux to be AHCT, for speed, where the demux might have only one or two loads.
I don't have any information on HOW they do the select, but it seems to me that if the RAM CS is generated asynchronous to the clock, 6502 bus style, and only the RE/OE synchronized to the bus, there ought to be enough room to fit the CS latencies of the SRAM into both the read and write cycles.
I guess if you put A8-A12 and A15 through the inputs of a dual 3-1 NAND and A13/A14 through two line driver lines (1 level), OR the four outputs (two levels), and feed that into a 3-8 demux with R/W and PHI2, that decoder (3rd level) gives you separate IO-OE, IO-WE, RAM/ROM-OE and RAM/ROM-WE. The OE and WE slew according to the propagation delay of the final demux, on both pull down and pull up, since the PHI2 transition low will be the driver for pulling whichever write/output enable line low, and the same for PHI2 transition high.
With Memory-OE and Memory-WE not generated for the I/O page, you wouldn't need to worry about the I/O page when generating the Memory CS ... just decode %000xxxxx - %100xxxxx as Low RAM, %101xxxxx as High RAM, and %110xxxxx - %111xxxxx as ROM.