53 minutes ago, rje said:
Right. The way I look at it, it would be nice if it could simply replace the 65C02, with no other changes. And I figure that was the original thought as well -- "can it just be plugged in and used like a super-powered 6502?" And the answer (based on video #2) was: probably not without annoying and/or expensive extra work. Since the system had to work first, that and other options were scrapped. The decision makes sense. It would be nice if the current board, being stable, allowed some experimentation, but meh.
Technically, "not without finding out what the issue is with the Vera startup process". Since they are taking advantage of the early assert of the 6502 address lines, it is entirely possible that the two bus timings comply with the same read delays and write holds specs, but the actual timing is not the same, so the 6502 just slips in under the bar while the 65816 misses. For instance, Vera is faster than the system bus, and is internally not synchronous with the system bus, it may be that the Vera sometimes actually performs its read early enough in the cycle when the 6502 is actually in a settled state, irrespective of what the timing diagram says, and the 65816 data bus is an an ambiguous state between the bank assert and the data asset.
And it could be use of Rockwell opcodes which can easily be replaced at the cost of a handful of bytes and a handful of clock cycles.
After their long delay getting the Proto#2 board to boot up, they can quite reasonably conclude that they don't have the time to hammer that out. If it can be fixed up later so that an end user can drop in a 65816 and just go, well, so be it, but leave that until the original is out in the wild and more people who are more interested in it have a go at the problem.
ESPECIALLY since they are explicitly setting up the slots so that a board that is willing to go to the extra work required can take over as the bus master, so a 65816 bus master expansion card is always an option. That expansion card can play clock cycle games that the drop in replacement cannot play ... for instance, with a 25MHz frequency source and a FPGA with a 2x PLL, it can generate an asymmetric 8MHz clock cycle for the 65816, with a shorter PHI2=1 cycle and a longer PHI2=0 cycle, if the problem is data not being asserted soon enough in the motherboard system clock cycle.
Edit: Note that if using an FPGA as sketched above fixed the problem, it might be a single main chip board ... other than clock module, voltage translation and some resisters and caps ... since WDC also licenses a soft core of the 65816.