Reconsidering the 65816 (W65C816S)

rje · Post by **rje** » Fri Jul 23, 2021 5:02 pm

We've seen the videos.

We know it would be like starting over, because the system only works at 8Mhz.

Paul Scott Robson:

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About as much chance as it being personally delivered by Luke Skywalker I think. Timing is apparently an "issue"

Kevin Williams:

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Even though the system is designed to be a 65C02 based machine, I designed it such that a 65C816 will work electrically in the board. The KERNAL isn't a fan of the 816, so it would have to be running a different OS, but we wanted to make sure people had the option to do what they wanted with the system.

Stephen Horn:

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the '816 either has a conflicting opcode with the 65C02 that the kernel is using, or is expecting some new piece of memory to be mapped in a way that conflicts with what the kernel is doing, and the kernal is crashing or entering an infinite loop before it gets to VERA initialization.

Various people:

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I can't muster even a little nostalgia for [the 65816]

But.

Paul's argument haunts me PROBABLY ONLY because I am not a good assembly language programmer:

With a faster processor, I could write a reasonably performant P-Code interpreter. We could write Robotron (et al) in C, or a kind of Commodore-friendly STOS BASIC.

And keep everything else we've got. (Theoretically)

What Paul is saying is EASE OF USE goes up by an order of magnitude, IF processor capability improves.

rje · Post by **rje** » Fri Jul 23, 2021 5:29 pm

But it's not about Ease of Use, because this is what I expect would happen:

Tom:

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It only takes one extra chip to make it work as intended, and we wouldn't have the silly 4K banks. Instead, we'd have up to 16MB of RAM in 64K banks.

Capability is expanded into a full 16 bit system, and this probably ceases to have that particularly Commodore simple-retro draw.

rje · Post by **rje** » Fri Jul 23, 2021 5:32 pm

So in summary: if I want something that feels like a Commodore 8-bit machine, then I should be content with the 6502, and be happy that there's still a gigantic pile of RAM that I never had on the C64.

I do wish sound and sprites were "easier to use", but that's a different thread to create.

BruceMcF · Post by **BruceMcF** » Sat Jul 24, 2021 5:47 pm

On 7/24/2021 at 1:29 AM, rje said:

But it's not about Ease of Use, because this is what I expect would happen:

Tom: "It only takes one extra chip to make it work as intended, and we wouldn't have the silly 4K banks. Instead, we'd have up to 16MB of RAM in 64K banks."

Capability is expanded into a full 16 bit system, and this probably ceases to have that particularly Commodore simple-retro draw.

But popping a 65816 into the CPU socket won't add the "one extra chip", because it has to be in the motherboard. Popping a 65816 into the CPU socket in effect gives you a 65802 with slight bus incompatibilities (SYNC is replaced by VDA/VPA and IIRC the clock outputs are DNC and a reset input).

And a bus mastering 65816 card would be pretty much the same thing, though more room for circuitry to bridge the bus incompatibilities ... including masking out the bank address from the data lines. I would be entirely unsurprised if the problem in writing VERA is the bank on the data bus followed by the data confusing Vera in a way that is not an issue with the 65C02 write cycle. Nor would I be surprised if the bus cycles for some of the chips "work" with the 6502 but just make it, and small variations in actual read or write delays associated with the transition between bank mode and data mode make the timing too tight to work.

But if you can get a bus mastering card to work, you get the pcode interpreter with the accumulator in 8bit mode and indexes in 16bit mode, with ops ending with JMP NEXTOP or an eight byte NEXTOP macro:

NEXTOP: INY : LDA 0,Y : TAX : JMP (OP1,X)

The thing is: since it can run 6502 assembly code, can run the same pcode as the 6502, except faster, and can host a compatible ROMBASIC interpreter, except faster, and since assembly code can test whether it is running on a 6502 or 65816, it might actually work as a 3rd party enhancement.

Then it would only breaks running CX16 code if people use any of the four individual-bit-addressed operations in their assembled code, so it just needs "enough" of an install base so people shy away from doing that.

rje · Post by **rje** » Sun Jul 25, 2021 6:45 am

Bruce, it sounds like that card would be nice to have!

Gromit337 · Post by **Gromit337** » Wed Jul 28, 2021 7:43 pm

A Commodore friendly STOS is called AMOS. ?

Perhaps those that don't like the choices being made for the X16 should look in to building there own 'dream' computer? Of course everyone else would be unhappy with >>>your<<< choices too, and ask why you can't build it differently? So there would be lots of incompatible computers... just like in the 1980s. ?

paulscottrobson · Post by **paulscottrobson** » Thu Jul 29, 2021 9:58 am

14 hours ago, Gromit337 said:

A Commodore friendly STOS is called AMOS. ?

Perhaps those that don't like the choices being made for the X16 should look in to building there own 'dream' computer? Of course everyone else would be unhappy with >>>your<<< choices too, and ask why you can't build it differently? So there would be lots of incompatible computers... just like in the 1980s. ?

Already done it. Pondering a RiscV based design, a sort of modern Archimedes

BruceMcF · Post by **BruceMcF** » Thu Jul 29, 2021 12:06 pm

16 hours ago, Gromit337 said:

A Commodore friendly STOS is called AMOS. ?

Perhaps those that don't like the choices being made for the X16 should look in to building there own 'dream' computer? Of course everyone else would be unhappy with >>>your<<< choices too, and ask why you can't build it differently? So there would be lots of incompatible computers... just like in the 1980s. ?

Great for hardware folks. Not so great for us software folks. And, of course, the odds for most of us pulling together Dave's retro Dream Team are quite low.

But luckily, the degree of flexibility to swap in a 65816 IS part of the design choices being made for the X16. The open question is whether it can be done with a CPU swap, or whether a bus mastering expansion board is the only workable option. But the board is being built to be electrically compatible with a 65816, so if there is a issue putting it in the CPU socket, it's a more subtle problem.

Guybrush · Post by **Guybrush** » Thu Jul 29, 2021 1:19 pm

1 hour ago, BruceMcF said:

Great for hardware folks. Not so great for us software folks.

Well, we can always build an emulator for our non-existent dream computer. It wouldn't be much different from where we are right now with the X16 ?.

Kalvan · Post by **Kalvan** » Thu Jul 29, 2021 3:28 pm

1 hour ago, Guybrush said:

Well, we can always build an emulator for our non-existent dream computer. It wouldn't be much different from where we are right now with the X16 ?.

You could also learn some HDL and invest in a Tesirac DE-10 Nano, possibly a few hats and a case, and try to implement it as an FPGA softcore. Then, once the basic chipset is solidified, you can progress to the necessary OS, BIOS, Language, and Driver code, and then whatever peripheral and interface ports you want to add via USB and dongles. Once you get all that solidified, you've taken roughly 75% of the guesswork out of designing a motherboard. Then, assuming you've stuck to (relatively) available chips in your softcore, you can either send the Gerber file you've confident enough with to PCB Way, or raise money and invest in a Nano-Dimension Dragonfly PCB 3D Printer, and begin assembling and testing prototype boards...