Search found 29 matches

by spargue
Thu Jul 27, 2023 1:53 pm
Forum: CX16 Hardware Support
Topic: FLIR baseline on Development Board
Replies: 11
Views: 14114

Re: FLIR baseline on Development Board

There may be "false-positives" due to reflections - for instance the metal casing around the keyboard/mouse are also a large reflective surface. At certain angles, I noticed the FLIR was "seeing itself" (or some other object in the reflection - such as my own body, which ends up...
by spargue
Thu Jul 20, 2023 10:22 pm
Forum: CX16 Hardware Support
Topic: FLIR baseline on Development Board
Replies: 11
Views: 14114

Re: FLIR baseline on Development Board

voidstar wrote: Tue Jul 18, 2023 7:58 am It's an older C2 model - 5+yrs now. 320x240 is all it can muster.
Move the camera closer to the board.
by spargue
Sun Jul 16, 2023 9:19 pm
Forum: CX16 Hardware Support
Topic: FLIR baseline on Development Board
Replies: 11
Views: 14114

Re: FLIR baseline on Development Board

This is really great work. Definitely shows the Yamaha could benefit from a heatsink to help extend its life.
by spargue
Sun Jul 02, 2023 6:42 pm
Forum: CX16 Hardware Support
Topic: Expansion slots
Replies: 58
Views: 3600374

Re: Expansion slots

Thanks Spargue! I’ve just sat down with a coffee and breakfast burrito at my local reservation breakfast shack to look at finalising this design when I saw your additional post here - much obliged. I hadn’t realised WE# needed to end a tad early so thanks for that. One thing I’m not sufficiently cl...
by spargue
Sun Jul 02, 2023 10:43 am
Forum: CX16 Hardware Support
Topic: Expansion slots
Replies: 58
Views: 3600374

Re: Expansion slots

On my PC now and not on my phone. Noticed the WE doesn't use the PHI2 edge. WE# needs to end slightly early to grab the data or it all collapses in a fuzzy way and you get bad writes. OE doesn't need this latch as its grabbed from the CPU internally on PHY2 I'd recommend some inline resistors on the...
by spargue
Sat Jul 01, 2023 10:24 pm
Forum: CX16 Hardware Support
Topic: Expansion slots
Replies: 58
Views: 3600374

Re: Expansion slots

Just so I'm clear from having followed this interesting & spirited discussion... If I WRITE to the banked ROM space for banks above #0-#31 and I have an expansion card with RAM mapped in to the ROM space, the data that is written by the CPU will actually be stored in the RAM, assuming I've wire...
by spargue
Sat Jul 01, 2023 10:20 pm
Forum: CX16 Hardware Support
Topic: Expansion slots
Replies: 58
Views: 3600374

Re: Expansion slots

Just so I'm clear from having followed this interesting & spirited discussion... If I WRITE to the banked ROM space for banks above #0-#31 and I have an expansion card with RAM mapped in to the ROM space, the data that is written by the CPU will actually be stored in the RAM, assuming I've wire...
by spargue
Thu Jun 29, 2023 3:34 pm
Forum: CX16 Hardware Support
Topic: Access to banked memory by expansion cards
Replies: 21
Views: 20867

Re: Access to banked memory by expansion cards

I'm the one that proposed using the VPB signal as an additional reset to the ROM bank latch and I looked at it fairly closely. Ultimately the decision was VPB as the only signal, which I disagree with but that's because I'd like an advanced debugger to insert itself after reset but before the CPU s...
by spargue
Thu Jun 29, 2023 7:53 am
Forum: CX16 Hardware Support
Topic: Access to banked memory by expansion cards
Replies: 21
Views: 20867

Re: Access to banked memory by expansion cards

Do expansion cards of any/all types, whether using the dedicated IO slots or accessing the full 64K address space seen by the CPU also get to 'see' the same banked ROM & RAM as the CPU does? I'm working on an expansion card design that could really do with accessing at least one of the 8K RAM b...
by spargue
Wed Jun 28, 2023 11:23 pm
Forum: CX16 Hardware Support
Topic: Access to banked memory by expansion cards
Replies: 21
Views: 20867

Re: Access to banked memory by expansion cards

I might know where the confusion is coming from. 4 latch is now value before entering ISR (not bank 0), but ISR is still running assuming it's bank 0. The very beginning of the ISR, which is responsible for reading $0001, pushing it onto the stack, and setting $0001 to zero, is executing out of RAM...