Commander X16

There are actually at least two problems with this idea. One of them is keeping track of data port addresses, as Ed already mentioned. The other is: since DATA0 and DATA1 have separate address registers, pushing more than one byte to this "stack" would require you to set the read address e...

are you sure you couldn't have worded that unoriginallity claim better? might want to be a bit careful with that mallet lest you drive away some contributors... if i didn't know any better your words could seem like mocking his mere attempt. I'm pretty sure I couldn't have, but hey, that's just me....

The "Sentinel 65X" guy seems to be reinventing the Commander X16 Phase 2 (which should be way cheaper than Phase 1) while patting himself on the back for being so smart.

Wow, that's quite a surprise to me, but indeed that's exactly what's causing the problem. After the lines of code that establish VERA control and VRAM addr, I changed my logic to loop-and-store-to-RAM, then loop over RAM and print. You could have also used the other VERA data port (VERA_data1) for ...

Since no one from the team replied to my question on another topic, I'll repeat it here: I have a (stupid?) question for the people who worked on VERA FX, so here it goes: Why is there no option to read the entire 32-bit cache in one read operation, since there is an option to write it in one operat...

Ed Minchau wrote: ↑Fri Aug 25, 2023 11:25 pm If you're using VERA channel 0 or 1, that STA is also 4 cycles, since it's going to an absolute address.

You're absolutely right, I was probably thinking of standard loops and indexed addressing. That means that the simple non-unrolled loop would be 11 cycles per 4 bytes, which is even better

I have a (stupid?) question for the people who worked on VERA FX, so here it goes: Why is there no option to read the entire 32-bit cache in one read operation, since there is an option to write it in one operation? It would allow for near-DMA speeds when copying data within the video RAM. LDA DATA0...

I don't think it's an emulator optimization. A read is a read and takes X cycles now or somewhere down the line. Yes, there should be some tiny gain if memory is read immediately after incrementing the address just because the address (or in the case of the emulator, an offset into the VERA memory b...

You mean I can change one of the other colors to black? I do not know how to do that. The color palette is in VERA's memory at $1FA00-$1FBFF, two bytes (12 bits, actually) for each entry. So, to set the color #N to black, simply set $1FA00 + (N * 2) and $1FA00 + (N * 2 + 1) to 0 In BASIC, that woul...

There's nothing stopping you from defining any of the colors #1-#15 as black.