Appendix B:
alphabetical list of 65c02 commands

This table lists all of the 65c02 commands in alphabetical order, including the addressing mode, opcode, 4-character notation used by the META/L assembly language editor, standard notation, number of bytes required, number of clock cycles, and the flags affected by each command.

There are 25 "pseudocommands" that allow branching to an address rather than relative branching; these commands do not exist on the 65c02 but are included in the editor, which converts the branch to a relative address automatically. In editor display mode 1 branches are shown as if they were these pseudocommands, but in editor display mode 2 they are shown as they are actually stored in memory, as the standard relative branches. These pseudocommands are shown with the addressing mode of {absolute}, with what would be the standard notation in curly braces {}, if these were real commands instead of stuff I made up.

notes:

ADC

add with carry
flag
effect
C
set if overflow in bit 7
Z
set if A = 0
V
set if sign bit is incorrect
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
69
ADC#
ADC #
2
2(b)
Zero Page
65
ADC0
ADC zp
2
3(b)
Zero Page,X
75
ADCZ
ADC zp,X
2
4(b)
Absolute
6D
ADCA
ADC abs
3
4(b)
Absolute,X
7D
ADCX
ADC abs,X
3
4(ab)
Absolute,Y
79
ADCY
ADC abs,Y
3
4(ab)
(Indirect,X)
61
ADC+
ADC (zp,X)
2
6(b)
(Indirect),Y
71
ADC-
ADC (zp),Y
2
5(ab)
(Indirect ZP)
72
ADC/
ADC (zp)
2
5(b)

AND

logical AND
flag
effect
Z
set if A = 0
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
29
AND#
AND #
2
2
Zero Page
25
AND0
AND zp
2
3
Zero Page,X
35
ANDZ
AND zp,X
2
4
Absolute
2D
ANDA
AND abs
3
4
Absolute,X
3D
ANDX
AND abs,X
3
4(a)
Absolute,Y
39
ANDY
AND abs,Y
3
4(a)
(Indirect,X)
21
AND+
AND (zp,X)
2
6
(Indirect),Y
31
AND-
AND (zp),Y
2
5(a)
(Indirect ZP)
32
AND/
AND (zp)
2
5

ASL

arithmetic shift left
flag
effect
C
set to contents of old bit 7
Z
set if A = 0
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
0A
ASLI
ASL Acc
1
2
Zero Page
06
ASL0
ASL zp
2
5
Zero Page,X
16
ASLZ
ASL zp,X
2
6
Absolute
0E
ASLA
ASL abs
3
6
Absolute,X
1E
ASLX
ASL abs,X
3
6(a)

BBR

branch on bit reset
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
ZP, relative
0F
BBR0
BBR0 zp,rel
3
5
{ZP, absolute}
{ 0F}
BR0A
{BBR0 zp,abs}
3
5
ZP, relative
1F
BBR1
BBR1 zp,rel
3
5
{ZP, absolute}
{ 1F}
BR1A
{BBR1 zp,abs}
3
5
ZP, relative
2F
BBR2
BBR2 zp,rel
3
5
{ZP, absolute}
{ 2F}
BR2A
{BBR2 zp,abs}
3
5
ZP, relative
3F
BBR3
BBR3 zp,rel
3
5
{ZP, absolute}
{ 3F}
BR3A
{BBR3 zp,abs}
3
5
ZP, relative
4F
BBR4
BBR4 zp,rel
3
5
{ZP, absolute}
{ 4F}
BR4A
{BBR4 zp,abs}
3
5
ZP, relative
5F
BBR5
BBR5 zp,rel
3
5
{ZP, absolute}
{ 5F}
BR5A
{BBR5 zp,abs}
3
5
ZP, relative
6F
BBR6
BBR6 zp,rel
3
5
{ZP, absolute}
{ 6F}
BR6A
{BBR6 zp,abs}
3
5
ZP, relative
7F
BBR7
BBR7 zp,rel
3
5
{ZP, absolute}
{ 7F}
BR7A
{BBR7 zp,abs}
3
5

BBS

branch on bit set
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
ZP, relative
8F
BBS0
BBS0 zp,rel
3
5
{ZP, absolute}
{ 8F}
BS0A
{BBS0 zp,abs}
3
5
ZP, relative
9F
BBS1
BBS1 zp,rel
3
5
{ZP, absolute}
{ 9F}
BS1A
{BBS1 zp,abs}
3
5
ZP, relative
AF
BBS2
BBS2 zp,rel
3
5
{ZP, absolute}
{ AF}
BS2A
{BBS2 zp,abs}
3
5
ZP, relative
BF
BBS3
BBS3 zp,rel
3
5
{ZP, absolute}
{ BF}
BS3A
{BBS3 zp,abs}
3
5
ZP, relative
CF
BBS4
BBS4 zp,rel
3
5
{ZP, absolute}
{ CF}
BS4A
{BBS4 zp,abs}
3
5
ZP, relative
DF
BBS5
BBS5 zp,rel
3
5
{ZP, absolute}
{ DF}
BS5A
{BBS5 zp,abs}
3
5
ZP, relative
EF
BBS6
BBS6 zp,rel
3
5
{ZP, absolute}
{ EF}
BS6A
{BBS6 zp,abs}
3
5
ZP, relative
FF
BBS7
BBS7 zp,rel
3
5
{ZP, absolute}
{ FF}
BS7A
{BBS7 zp,abs}
3
5

BCC

branch if carry clear (i.e. if C=0)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
90
BCC#
BCC rel
2
2(ac)
{absolute}
{ 90}
BCCA
{BCC abs}
2
2(ac)

BCS

branch if carry set (i.e. if C=1)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
B0
BCS#
BCS rel
2
2(ac)
{absolute}
{ B0}
BCSA
{BCS abs}
2
2(ac)

BEQ

branch if equal (i.e. if Z=1)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
F0
BEQ#
BEQ rel
2
2(ac)
{absolute}
{ F0}
BEQA
{BEQ abs}
2
2(ac)

BIT

bit test
flag
effect
Z
set if the result of the AND is zero
V
set to bit 6 of the memory value
N
set to bit 7 of the memory value
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
89
BIT#
BIT #
2
2
Zero Page
24
BIT0
BIT zp
2
3
Zero Page,X
34
BITZ
BIT zp,X
2
4
Absolute
2C
BITA
BIT abs
3
4
Absolute,X
3C
BITX
BIT abs,X
3
4(a)

BMI

branch if minus (i.e. if N=1)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
30
BMI#
BMI rel
2
2(ac)
{absolute}
{ 30}
BMIA
{BMI abs}
2
2(ac)

BNE

branch if not equal (i.e. if Z=0)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
D0
BNE#
BNE rel
2
2(ac)
{absolute}
{ D0}
BNEA
{BNE abs}
2
2(ac)

BPL

branch if positive (i.e. if N=0)
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
10
BPL#
BPL rel
2
2(ac)
{absolute}
{ 10}
BPLA
{BPL abs}
2
2(ac)

BRA

branch always
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
80
BRAN
BRA rel
2
3(a)
{absolute}
{ 80}
BRAA
{BRA abs}
2
2(ac)

BRK

force interrupt
flag
effect
B
set to 1
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
implied
00
BRK0
BRK imp
1
7

BVC

branch if overflow clear
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
50
BVC#
BVC rel
2
2(ac)
{absolute}
{ 50}
BVCA
{BVC abs}
2
2(ac)

BVS

branch if overflow set
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
relative
70
BVS#
BVS rel
2
2(ac)
{absolute}
{ 70}
BVSA
{BVS abs}
2
2(ac)

CLC

clear carry flag
flag
effect
C
set to 0
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
implied
18
CLCF
CLC imp
1
2

CLD

clear decimal mode flag
flag
effect
D
set to 0
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
implied
D8
CLDM
CLD imp
1
2

CLI

clear interrupt disable
flag
effect
I
set to 0
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
implied
58
CLID
CLI imp
1
2

CLV

clear overflow flag
flag
effect
V
set to 0
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
implied
B8
CLVF
CLV imp
1
2

CMP

compare accumulator
flag
effect
C
set if A>=M
Z
set if A=M
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
C9
CMP#
CMP #
2
2
Zero Page
C5
CMP0
CMP zp
2
3
Zero Page,X
D5
CMPZ
CMP zp,X
2
4
Absolute
CD
CMPA
CMP abs
3
4
Absolute,X
DD
CMPX
CMP abs,X
3
4(a)
Absolute,Y
D9
CMPY
CMP abs,Y
3
4(a)
(Indirect,X)
C1
CMP+
CMP (zp,X)
2
6
(Indirect),Y
D1
CMP-
CMP (zp),Y
2
5(a)
(Indirect ZP)
D2
CMP/
CMP (zp)
2
5

CPX

compare X register
flag
effect
C
set if X>=M
Z
set if X=M
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
E0
CPX#
CPX #
2
2
Zero Page
E4
CPX0
CPX zp
2
3
Absolute
EC
CPXA
CPX abs
3
4

CPY

compare Y register
flag
effect
C
set if Y>=M
Z
set if Y=M
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
C0
CPY#
CPY #
2
2
Zero Page
C4
CPY0
CPY zp
2
3
Absolute
CC
CPYA
CPY abs
3
4

DEC

decrement memory
flag
effect
Z
set if result is zero
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
3A
DECI
DEC Acc
1
2
Zero Page
C6
DEC0
DEC zp
2
5
Zero Page,X
D6
DECZ
DEC zp,X
2
6
Absolute
CE
DECA
DEC abs
3
6
Absolute,X
DE
DECX
DEC abs,X
3
7

DEX

decrement X register
flag
effect
Z
set if X is zero
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
CA
DEXI
DEX imp
1
2

DEY

decrement Y register
flag
effect
Z
set if Y is zero
N
set if bit 7 of Y is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
88
DEYI
DEY imp
1
2

EOR

exclusive OR
flag
effect
Z
set if A is zero
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
49
EOR#
EOR #
2
2
Zero Page
45
EOR0
EOR zp
2
3
Zero Page,X
55
EORZ
EOR zp,X
2
4
Absolute
4D
EORA
EOR abs
3
4
Absolute,X
5D
EORX
EOR abs,X
3
4(a)
Absolute,Y
59
EORY
EOR abs,Y
3
4(a)
(Indirect,X)
41
EOR+
EOR (zp,X)
2
6
(Indirect),Y
51
EOR-
EOR (zp),Y
2
5(a)
(Indirect ZP)
52
EOR/
EOR (zp)
2
5

INC

increment memory
flag
effect
Z
set if result is zero
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
1A
INCI
INC Acc
1
2
Zero Page
E6
INC0
INC zp
2
5
Zero Page,X
F6
INCZ
INC zp,X
2
6
Absolute
EE
INCA
INC abs
3
6
Absolute,X
FE
INCX
INC abs,X
3
7

INX

increment X register
flag
effect
Z
set if X is zero
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
E8
INXI
INX imp
1
2

INY

increment Y register
flag
effect
Z
set if Y is zero
N
set if bit 7 of Y is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
C8
INYI
INY imp
1
2

JMP

jump
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Absolute
4C
JMPA
JMP abs
3
3
Indirect
6C
JMPI
JMP ind
3
6
(Absolute,X)
7C
JMPX
JMP (abs,X)
3
6

JSR

jump to subroutine
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Absolute
20
JSRA
JSR abs
3
6

LDA

load accumulator
flag
effect
Z
set if A is zero
N
set if bit 7 of A is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
A9
LDA#
LDA #
2
2
Zero Page
A5
LDA0
LDA zp
2
3
Zero Page,X
B5
LDAZ
LDA zp,X
2
4
Absolute
AD
LDAA
LDA abs
3
4
Absolute,X
BD
LDAX
LDA abs,X
3
4(a)
Absolute,Y
B9
LDAY
LDA abs,Y
3
4(a)
(Indirect,X)
A1
LDA+
LDA (zp,X)
2
6
(Indirect),Y
B1
LDA-
LDA (zp),Y
2
5(a)
(Indirect ZP)
B2
LDA/
LDA (zp)
2
5

LDX

load X register
flag
effect
Z
set if X is zero
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
A2
LDX#
LDX #
2
2
Zero Page
A6
LDX0
LDX zp
2
3
Zero Page,Y
B6
LDXZ
LDX zp,Y
2
4
Absolute
AE
LDXA
LDX abs
3
4
Absolute,Y
BE
LDXY
LDX abs,Y
3
4(a)

LDY

load Y register
flag
effect
Z
set if Y is zero
N
set if bit 7 of Y is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
A0
LDY#
LDY #
2
2
Zero Page
A4
LDY0
LDY zp
2
3
Zero Page,X
B4
LDYZ
LDY zp,X
2
4
Absolute
AC
LDYA
LDY abs
3
4
Absolute,X
BC
LDYX
LDY abs,X
3
4(a)

LSR

logical shift right
flag
effect
C
set to contents of old bit 0
Z
set if result is zero
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
4A
LSRI
LSR Acc
1
2
Zero Page
46
LSR0
LSR zp
2
5
Zero Page,X
56
LSRZ
LSR zp,X
2
6
Absolute
4E
LSRA
LSR abs
3
6
Absolute,X
5E
LSRX
LSR abs,X
3
6(a)

NOP

no operation
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
EA
NOPE
NOP imp
1
2

ORA

logical inclusive OR
flag
effect
Z
set if A is zero
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
09
ORA#
ORA #
2
2
Zero Page
05
ORA0
ORA zp
2
3
Zero Page,X
15
ORAZ
ORA zp,X
2
4
Absolute
0D
ORAA
ORA abs
3
4
Absolute,X
1D
ORAX
ORA abs,X
3
4(a)
Absolute,Y
19
ORAY
ORA abs,Y
3
4(a)
(Indirect,X)
01
ORA+
ORA (zp,X)
2
2
(Indirect),Y
11
ORA-
ORA (zp),Y
2
5(a)
(Indirect ZP)
12
ORA/
ORA (zp)
2
5

PHA

push accumulator
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
48
PHAI
PHA imp
1
3

PHP

push processor status
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
08
PHPI
PHP imp
1
3

PHX

push X register
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
DA
PHXI
PHX imp
1
3

PHY

push Y register
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
5A
PHYI
PHY imp
1
3

PLA

pull accumulator
flag
effect
Z
set if A=0
N
set if bit 7 of A is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
68
PLAI
PLA imp
1
4

PLP

pull processor status
flag
effect
C
set from stack
Z
set from stack
I
set from stack
D
set from stack
B
set from stack
V
set from stack
N
set from stack
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
28
PLPI
PLP imp
1
4

PLX

pull X register
flag
effect
Z
set if X=0
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
FA
PLXI
PLX imp
1
4

PLY

pull Y register
flag
effect
Z
set if Y=0
N
set if bit 7 of Y is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
7A
PLYI
PLY imp
1
4

RMB

reset memory bit
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
07
RMB0
RMB0 zp
2
5
Zero Page
17
RMB1
RMB1 zp
2
5
Zero Page
27
RMB2
RMB2 zp
2
5
Zero Page
37
RMB3
RMB3 zp
2
5
Zero Page
47
RMB4
RMB4 zp
2
5
Zero Page
57
RMB5
RMB5 zp
2
5
Zero Page
67
RMB6
RMB6 zp
2
5
Zero Page
77
RMB7
RMB7 zp
2
5

ROL

rotate left
flag
effect
C
set to contents of old bit 7
Z
set if A=0
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
2A
ROLI
ROL Acc
1
2
Zero Page
26
ROL0
ROL zp
2
5
Zero Page,X
36
ROLZ
ROL zp,X
2
6
Absolute
2E
ROLA
ROL abs
3
6
Absolute,X
3E
ROLX
ROL abs,X
3
6(a)

ROR

rotate right
flag
effect
C
set to contents of old bit 0
Z
set if A=0
N
set if bit 7 of the result is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Accumulator
6A
RORI
ROR Acc
1
2
Zero Page
66
ROR0
ROR zp
2
5
Zero Page,X
76
RORZ
ROR zp,X
2
6
Absolute
6E
RORA
ROR abs
3
6
Absolute,X
7E
RORX
ROR abs,X
3
6(a)

RTI

return from interrupt
flag
effect
C
set from stack
Z
set from stack
I
set from stack
D
set from stack
B
set from stack
V
set from stack
N
set from stack
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
40
RTII
RTI imp
1
6

RTS

return from subroutine
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
60
RTSI
RTS imp
1
6

SBC

subtract with carry
flag
effect
C
set if overflow in bit 7
Z
set if A = 0
V
set if sign bit is incorrect
N
set if bit 7 is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Immediate
E9
SBC#
SBC #
2
2(b)
Zero Page
E5
SBC0
SBC zp
2
3(b)
Zero Page,X
F5
SBCZ
SBC zp,X
2
4(b)
Absolute
ED
SBCA
SBC abs
3
4(b)
Absolute,X
FD
SBCX
SBC abs,X
3
4(ab)
Absolute,Y
F9
SBCY
SBC abs,Y
3
4(ab)
(Indirect,X)
E1
SBC+
SBC (zp,X)
2
6(b)
(Indirect),Y
F1
SBC-
SBC (zp),Y
2
5(ab)
(Indirect ZP)
F2
SBC/
SBC (zp)
2
5(b)

SEC

set carry flag
flag
effect
C
set to 1
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
38
SECF
SEC imp
1
2

SED

set decimal mode flag
flag
effect
D
set to 1
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
F8
SEDM
SED imp
1
2

SEI

set interrupt disable
flag
effect
I
set to 1
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
78
SEID
SEI imp
1
2

SMB

set memory bit
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
87
SMB0
SMB0 zp
2
5
Zero Page
97
SMB1
SMB1 zp
2
5
Zero Page
A7
SMB2
SMB2 zp
2
5
Zero Page
B7
SMB3
SMB3 zp
2
5
Zero Page
C7
SMB4
SMB4 zp
2
5
Zero Page
D7
SMB5
SMB5 zp
2
5
Zero Page
E7
SMB6
SMB6 zp
2
5
Zero Page
F7
SMB7
SMB7 zp
2
5

STA

store accumulator
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
85
STA0
STA zp
2
3
Zero Page,X
95
STAZ
STA zp,X
2
4
Absolute
8D
STAA
STA abs
3
4
Absolute,X
9D
STAX
STA abs,X
3
5
Absolute,Y
99
STAY
STA abs,Y
3
5
(Indirect,X)
81
STA+
STA (zp,X)
2
6
(Indirect),Y
91
STA-
STA (zp),Y
2
6
(Indirect ZP)
92
STA/
STA (zp)
2
5

STP

stop
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
DB
STOP
STP imp
1
3

STX

store X register
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
86
STX0
STX zp
2
3
Zero Page,Y
96
STXZ
STX zp,Y
2
4
Absolute
8E
STXA
STX abs
3
4

STY

store Y register
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
84
STY0
STY zp
2
3
Zero Page,X
94
STYZ
STY zp,X
2
4
Absolute
8C
STYA
STY abs
3
4

STZ

Store zero in memory
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
64
STZ0
STZ zp
2
3
Zero Page,X
74
STZZ
STZ zp,X
2
4
Absolute
9C
STZA
STZ abs
3
4
Absolute,X
9E
STZX
STZ abs,X
3
5

TAX

transfer accumulator to X
flag
effect
Z
set if X=0
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
AA
TAXI
TAX imp
1
2

TAY

transfer accumulator to Y
flag
effect
Z
set if Y=0
N
set if bit 7 of Y is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
A8
TAYI
TAY imp
1
2

TRB

test and reset bits
flag
effect
Z
set if the memory value held any of the specified bits
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
14
TRB0
TRB zp
2
5
Absolute
1C
TRBA
TRB abs
3
6

TSB

test and set bits
flag
effect
Z
set if the memory value held any of the specified bits
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Zero Page
04
TSB0
TSB zp
2
5
Absolute
0C
TSBA
TSB abs
3
6

TSX

transfer stack pointer to X
flag
effect
Z
set if X=0
N
set if bit 7 of X is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
BA
TSXI
TSX imp
1
2

TXA

transfer X to accumulator
flag
effect
Z
set if A=0
N
set if bit 7 of A is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
8A
TXAI
TXA imp
1
2

TXS

transfer X to stack pointer
flag
effect
none
none
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
9A
TXSI
TXS imp
1
2

TYA

transfer Y to accumulator
flag
effect
Z
set if A=0
N
set if bit 7 of A is set
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
98
TYAI
TYA imp
1
2

WAI

wait for interrupt
flag
effect
B
set to 1
addressing mode
opcode
4 char
standard
#bytes
#cycles(notes)
Implied
CB
WAIT
WAI imp
1
3