Commander X16

Scanline register in NTSC mode is not behaving like in the documentation. 240p is not interlaced. Adding +1 to the current scanline register for the next IRQ LINE interrupt shouldn't work since bit 0 is ignored, still every other frame it does work, and the other frame it does just the same as when...

I still don't quite understand what is is that you are saying is wrong. In 240p mode, only even lines are ever drawn onto the CRT. Internally it is a minor modification to 480i such that 263 full lines are always rendered causing the second field, which would normally start rendering odd lines, to a...

I made an experimental change... While it did move the location where the background color changes earlier, it was still in the visible area of the display. I did not expect this; it should have given... It has been known for some time that there is no time to make it to our own interrupt code, but...

I made an experimental change this weekend that moved the timing of the line interrupt to the end of active display. I ran it using the test program here. While it did move the location where the background color changes earlier, it was still in the visible area of the display. I did not expect this...

De minimis has been eliminated for imports from China, not other countries.

https://www.whitehouse.gov/fact-sheets/ ... id-crisis/

Always check the datasheet on these things before making assumptions about how performant memory is. The APS6408L is a *synchronous* pseudo SRAM with a highly multiplexed ADQ bus and a tRC latency of 60ns. Strictly speaking, there is no way to meet the datasheet minimums at anything faster than 8MHz...

The biggest problem with SDRAM (or DRAM) is that memory access latency is relatively long and that latency has not changed much in the past couple of decades. E.g. an SDRAM with CAS latency of 2 typically has a tRC of 9-10 cycles. At 200MHz, that's 45-50 ns between random memory accesses. Their sequ...

I hope that I get this right, I'm interpreting the Verilog code for VERA: 1. Reset the accumulator (read from $9F29, DCSEL=6; or write bit 7 of $9F2C, DSCEL=2) 2. Perform first multiply 3. Add that product to the accumulator (read from $9F2A, DCSEL=6; or write bit 6 of $9F2C, DCSEL=2) 4. Perform you...

As I recall the DMA on NES lived in the 2A03 CPU.

It would be possible to have hardware external to VERA do DMA writes. The current VERA firmware could not keep up with writes every cycle so a delay would be necessary.

Wouldn't the internet be a more ideal software distribution medium? Modern flash storage is pretty stable; data loss is fairly unusual in my experience. I cannot think of a time when I lost data on one due to charge degradation. CDs and DVDs have well known sources of data loss: https://en.wikipedia...